Here is the detailed course descriptor, with a breakdown of prerequisites, lectures, grading policy, test dates, etc. Here are three questions that you can use to check if you are ready for the class.

IMPORTANT DATES: Wednesday Sep. 20 (Lab 1 due); Wednesday Oct. 11 (Lab 2 due); Tuesday Oct. 17 (Midterm 1); Wednesday Nov. 1 (Lab 3 due); Tuesday Nov. 21 (Midterm 2)

Please fill out this small bio; it really helps me get to know the class better.

• Class Notes

  I will use, with minor modifications, the excellent notes prepared by David Harris to accompany the text. I've listed the corresponding sections of the book, but you should read more broadly. In particular, I would like you to pay particular emphasis to the "Pifalls and Fallacies" section concluding each chapter.
  • Introduction (1.1-1.3)
  • CMOS Fabrication and its implications (1.3, 3.1-3.5)
  • Elementary CMOS logic design and layout (1.4-1.5.5)
    • See Chris Mack's page for a nice litho tutorial.
  • MOS Device Equations (2.1-2.3.1)
  • CMOS Logic: Quantiative Analysis (2.3.2-2.6, 4.2)
  • Logical Effort (4.3)
  • Simulating Circuits (5 - we won't cover this material, but you may want to brush up on it)
  • Interconnect (4.5-4.6)
  • Adders (10.1-10.2)
    • Mathematical treatment of parallel prefix computation
  • Advanced static gate design (6.1-6.2.1)
  • Alternatives to static logic (6.2.2-6.2.5, 6.4-6.6)
  • Sequential Design (7.1-7.5)
  • SRAMs (11.1-11.2)
  • CAMs, ROMs, and PLAs (11.4-11.7)
  • Datapath (10.3-10.10)
  • MOS Devices in DSM (2.4)
  • Circuit Pitfalls (6.3)
  • Test (4.8, 9)
  • Low Power (6, with an emphasis on 6.5)
  • Design for Skew (7.5-7.6, 12.5)
  • Packaging, Power Supplies, and I/O (12.2-12.4)
  • Scaling and Economics (4.9, and 8.5)
  • Evolution of Intel processors
  • Case Study: Cell Processor
    • An article detailing the cell processor
  • Review

• Teaching Assistants

  • Office Hours

• Homework

  Homework problems, solutions, and issues are linked here.

• Sample midterms

  • Midterm 1 questions
  • Midterm 2 questions (Figures for faulty circuits are from the Circuit Pitfalls lecture). The undergrad test is linked here.

• Projects

  • Lab 1: Layout
  • Lab 2: ALU design
  • Lab 3: HDL coding and verification
  • Final project: Designing an IP core
    • Sample report 1: MIPS Part 1, MIPS Part 2
    • Sample report 2: SRAM
    • Sample report 3: Cordic Part 1, Cordic Part 2
    • Sample report 4: Crossbar
    • Writing guidelines

• Resources

  • Microwind is a nice public domain tool for VLSI design.
  • Read about the latest trends in VLSI design at EE Times; Deepchip.com is a great resource for VLSI CAD.
  • You can send email to the entire class by addressing your mail to ee360r-16860 AT ece DOT utexas DOT edu
  • Document viewing:
    • Use Aladdin Ghostscript to view postscript on Win95/WinNT.
    • Use Adobe Acrobat to view pdf files; you can download Acrobat here
    • You can convert Postscript to PDF via ps2pdf
  • The ECE Learning Resource Center.
  • Getting started with UNIX, vi, g++, gdb.