Homeworks

• Homework 0: Fill out the biodata form pdf
• Homework 1: Boolean functions pdf
• Homework 2: 2-level minimization pdf
• Homework 3: BDDspdf
• Homework 4: Implementing a BDD packagepdf (Set the environment variable VIS_LIBRARY_PATH to /home/projects/ece/verif/v-1.0/vis-1.2/share to pick up the scripts needed to read blif files)
• Midterm from 1999
  • Here is my implementations:utaTst.c
  • Here is are some notes on common programming mistakes I saw:Dos/Donts
• Homework 5: Multi-level minimization pdf
• Homework 6: Don't cares, and Technology mapping pdf
• Midterm 2 from 1998
• Homework 7: Timing Optimizationpdf

Lecture Material

• Introduction
• Boolean functions
• Sum-of-Product representations
• Conjunctive normal forms
• Exact 2-level minimization: Quine-McCluskey
• Heuristic 2-level minimization: ESPRESSO (Thanks to Fadi and Scott for helping create the pdf)
• BDDs (Note: I fixed small typoes on pages 5, 15, and 19, new slides uploaded 10.2.03)
• General Boolean circuits
• Factored forms
• Algebraic division
• Boolean division
• Using don't cares to optimize multilevel logic
• Technology mapping
• Timing analysis
• Timing optimization
• Sequential synthesis
• Equivalence checking

Projects

• Descriptor

Miscellaneous Handouts

• Course Descriptor
• How to do proofs

Resources

• You can read about the latest trends in VLSI design at EE Times; Deepchip.com is a great resource for VLSI CAD. The verification guild focuses on design verification.
• Don Thomas has a great Introduction to Verilog
• You can send email to the entire class by addressing your mail to ee82m-15503 AT ece DOT utexas DOT edu
• A nice user manual for SIS
• Other classes
  • Logic synthesis class taught at UC Berkeley
  • Jacob Abraham's class: 360R
  • Some excellent notes on VLSI design.
• Document viewing:
  • Use Aladdin Ghostscript to view postscript on Win95/WinNT.
  • Use Adobe Acrobat to view pdf files; you can download Acrobat here
  • You can convert Postscript to PDF via ps2pdf
• The ECE Learning Resource Center.