• Unit 1: January 23-24
• Unit 2: February 20-21
• Unit 3: March 13-14
• Unit 4: April 3-4
  • Test 1: Start of Unit, 2 hours. Topics 2009; sample Midterm 1, 2006.
• Unit 5: May 15-16
  • Test 2: End of Unit, 2 hours. Topics 2009; sample Midterm 2, 2007.

There will be 4 written homeworks, and 4 labs. Homeworks and labs will be staggered. A lab which is assigned in Unit-i will be due on Sunday following Unit-(i+1), 23:59 hours, the exception being the final lab, which will be due one week before Unit 5.

• Introduction Course syllabus
• Digital CMOS
• Analog CMOS ADC and DAC terminology: Link 1, Link 2
• Communication Systems Theory - also see my notes, and some more readings. Notes for CDMA.
• Fast convolution using the FFT: we'll largely draw on Cormen, Leiserson, Rivest, and Stein's “Introduction to Algorithms” text, specifically Chapter 32. Here are some figures, and a talk describing the state-of-the-art in software FFTs, and the project homepage
• Computing trignometric functions using CORDIC - some comments.
• Digital filtering in hardware: we'll be using Parhi's book - his notes are are online, and in some respects are a little easier to read. Here are some of the figures we'll use for illustration.
  • Introduction, Iteration bound (Ch1, Ch2)
  • Pipelining & Parallel Processing (Ch 3)
  • Retiming (Ch 4 - we'll go in less detail; a simpler description of algorithms for retiming)
  • Unfolding, Folding (Ch 5, 6)
  • Recursive and Adaptive Filters (Ch 10)
    • Here is a quick-and-dirty introduction to stability theory for IIR filters.
    • Here are some figures illustrating the effects of incomplete pole zero cancellation; the source files are iir_finite_df1.m, iir_infinite.m, quant_and_saturate.m, and run_iir_sim.m.
    • Here is an old but clear paper on implememting adaptive equalizers for disk drive read channels.
  • Numerical strength reduction (Ch 15)
  • Scaling and Roundoff Noise (Ch 11)
    • A toolbox for computing wordlengths for filters by Kyungtae Han and Brian Evans
    • Here is a classic paper on the impact of round-off noise on parallel, cascade, and lattice filter structures, all implementing the same transfer function.
• Error correcting codes: my notes are mostly from “Error Correcting Codes” by Lin and Costello. Some comments.
• Switching: a short overview of hardware issues in switch design (4-to-a-page)
• Recap: a quick walk-through of what we covered in the class
• Programmable DSPs Mike Warner's overview of DSP architectures
• Adaptive Filtering for Noise Cancellation Slides from Jay Fletcher's (ECD MS 2006) talk
• Wireless Communications: From Systems to Silicon Dr Raghu Rao (Xilinx) on the design and implementation of a complex communication protocol

Diptendu Ghosh, 512-573-3916, , Office: ENS 507

Submission Guidelines

• Hardcopy: preferred
• Softcopy: email to
  • Subject: [Yourname_VLSI_COMM_HW_#] or [Yourname_VLSI_COMM_LAB_#]
  • Please attach a SINGLE file (.pdf, .zip, .doc, etc.) or send the web link to files.
  • Corey Thacker experienced a problem with Adobe Writer creating a pdf that was too big for the UT servers, which have an attachment size limit (8MB?). On advice from Henry Chang, he used bullzip to create a much smaller pdf which did go through.

(Some links may not be activated yet.)

All course related files can be found at here.

Please see the FAQ page on assignments frequently.

• Sample ECD MS reports from previous years, by Jacob Schneider, Dan Dankert, and Jay Fletcher
• Useful tools for prototyping communications systems:
  • The open source Ptolemy system from UCB can be used to simulate very sophisticated communication systems. (The SDF demos are particularly interesting.) Our local copy is described here
  • Labview from National Instruments: avaiable free for UT students; click here to download
  • Simulink and Matlab: available on the LRC machines; you can buy them at the campus computer store at a discounted price
  • The Microwind and Dsch VLSI design tools are good for small designs, e.g., determining the delay of an unbuffered 1mm wire in 0.13 micron TSMC CMOS, or the size of a full adder. You can download them here.
• Tutorials on filter synthesis
  • A nice tutorial on filter design
  • Going from a frequency domain definition of a filter to a time domain definition: IIR and FIR * A broad introduction to filters.
• Other classes
  • Bob Brodersen's class: 225C has a similar focus on filtering, with a more emphasis on analog/RF
  • Brian Evan's class: 345S solves many of the same problems as we do, but using software running on programmable DSPs
  • My own VLSI-1 class covers digital CMOS VLSI design
• Berkeley Design Technologies provides analysis on signal processing technology. They have a number of excellent reports on general purpose DSPs.
  • Their pocket guide to programmable DSPs is a great reference, and their report on the TI MMS320C64x fixed point DSP gives an interesting overview of programmable DSPs.
  • They also have developed a benchmark suite - 4 FIR filters, an IIR filter, 256 point FFT, 3 vector operations, a Viterbi decoder, a bit unpacker, and a program with lots of control. (There's a seperate OFDM benchmark.)
• Two high-level views of trends in implementing communication systems:
  • Bob Brodersen (UC Berkeley) Signal Processing in Future Radio Systems
  • Teresa Meng (Stanford) Digitally Assisted Analog Circuit Design for Communication SOCs
• Two relevant articles from Chip Design magazine:
  • From Algorithms to Artwork: an article on the relationship between RF design and DSP
  • Design FPGA-Based DSPs for Performance and Power: bringing DSP capability to FPGAs
• Interesting implementations
  • A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. JSSC, March 2004.
  • Design Considerations and Implementation of a DSP-Based Car-Radio IF Processor. JSSC, July 2004.
  • A single-chip MPEG-2 codec based on customizable media embedded processor. JSSC, March 2003.
  • All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. JSSC, December 2004.
  • A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN. JSSC, December 2004.
  • A Single-Chip CMOS Transceiver for 802.11a/b/g Wireless LANs. JSSC, December 2004.
  • A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. JSSC, November 2003.
  • embedded-processor-jssc-03.pdf|A VLIW processor with reconfigurable instruction set for embedded applications. JSSC, November 2003.
  • Take a look at this early paper on an all-digital CMOS radio; it makes extensive use of filter minimization techniques that we'll be discussing. (Incidentally, the second author, Henry Samueli, took these ideas and started Broadcom
• A graphical view of sampling