Note: As of 5.29.2009, I still don't have a list of student enrolled in this class. I've updated the due dates for assignments for 2009, but can't create your Wiki pages, so Assignment 0 is on hold. I'll be away over the weekend (5.29-5.31) and not able to read mail.
Update 6.1.2008: I've been told I will have the roster tomorrow (6.2.2009 - Tuesday), and I'll create accounts and mail each of you as soon as I receive the roster.
We will research the current state-of-the-art in industrial CMOS design, with an emphasis on the latest in circuit design techniques. Students will get a window into design styles and issues arising in real-world applications.
The course is targeted to students who are trying figure out what they want to do in circuit design. It will give you an opportunity to chase down a few interesting areas and see what fits. The exposure to a number of different topics should help you make choices in future projects and courses.
Insight into leading edge chip designs, and getting more “plugged in” to the current state of the industry
Training in how to go about referencing and reviewing papers from technical journals and conferences
Better perspectives on courses such as VLSI-II
We will perform an in-depth study of a number of state-of-the-art industrial CMOS designs. These designs will cover a broad range of applications including high-end microprocessors, communications, DSP, networking, embedded systems, datapath, and low-power. The selected designs will also illustrate a number of design styles (from full-custom to completely synthesized) and design constraints (e.g., low-power, fault tolerance, etc.). I have selected these designs based on a reading of recent issues of the IEEE Journal of Solid- State Circuits (JSSC). This journal is the pre-eminent forum for presenting in-depth technical details on real chips, and the papers describing the designs will be the starting point for our study.
As an alternative, with my approval, you can select a set of articles (IEEE papers, book chapters, vendor literature, etc.), focusing on a topic of interest to you. If there are any conferences or seminars that you are interested in attending and writing about, then that could replace a paper as well.
You will be required to write a report on each of the topics. It should include the following:
Context: what does the chip do, who are its customers and competitors, what were the constraints on the design, etc.
There are several resources you should use for this section:
Textbooks—Weste & Harris [3], Chandrakasan [1], and Rabaey [2]
Product application notes
Periodicals, including commercial ones such as EE Times, as well as more technical ones such as IEEE Spectrum
Technology: made when implementing the chip. Discuss both
Pay special attention to the key design decisions The article itself will be the main source for this section; you will need to also need to refer to the articles it cites, and the and textbooks.
Critique: describe what you feel are the strong features of the design, where you feel mistakes were made. (Think of yourself as a reviewer for the journal, who is being asked to give reasons for/against accepting the paper.) Use a mixture of common sense and the textbooks.
Your grade will be based solely on my evaluation of your reports—there will be no other written homework, tests, or labs.
I have made a couple of reports written by students over the past couple of years available as samples; they are linked at the bottom of this page. If you want to define your own set of topics and have a design component to your project, you will need to specify a reasonable evaluation policy.
Each of you will have a personal Wiki page with a password which you are to use for uploading homework. Detailed submission notes are linked here—the remarks on code/results are not relevant for this class.
Due 6.21.2009
A 65-nm Dual-Core Multithreaded Xeon Processor With 16-
MB L3 Cache. IEEE Journal of Solid State Circuits. IEEE Journal of Solid State Circuits.
The microarchitecture of the synergistic processor for a cell processor. IEEE Journal of Solid State Circuits. February 2006.
Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip IEEE Journal of Solid State Circuits. January 2008.
Design and Implementation of the POWER6 Microprocessor IEEE Journal of Solid State Circuits. January 2008.
Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing IEEE Journal of Solid State Circuits. January 2008.
Due 7.12.2009
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE Journal of Solid State Circuits. November 2003.
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O. IEEE Journal of Solid State Circuits. March 2003.
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process. IEEE Journal of Solid State Circuits. August 2006.
An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 mum CMOS Process IEEE Journal of Solid State Circuits. March 2008.
A 1.9 Gb/s 358 mW 16256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS IEEE Journal of Solid State Circuits. January 2008
Due 7.26.2009
Low leakage techniques for FPGAs. IEEE Journal of Solid State Circuits. July 2007.
A self-tuning DVS processor using delay-error detection and correction IEEE Journal of Solid State Circuits. April 2006.
Methods for true energy-performance optimization. IEEE Journal of Solid State Circuits. August 2004.
A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor. IEEE Journal of Solid State Circuits. August 2006.
AsAP: An Asynchronous Array of Simple Processors IEEE Journal of Solid State Circuits. March 2008.
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy IEEE Journal of Solid State Circuits. January 2008.
Due 8.2.2009
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. IEEE Journal of Solid State Circuits. August 2006.
A 9-
GHz 65-nm Intel Pentium 4 Processor Integer Execution Unit. IEEE Journal of Solid State Circuits. January 2007.
A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor. IEEE Journal of Solid State Circuits. April 2006.
A shared-well dual-supply-voltage 64-bit ALU. IEEE Journal of Solid State Circuits. March 2004.
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE Journal of Solid State Circuits. March 2006.
Implementation of the Cell Broadband Engine in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6
GHz at 1.3 V IEEE Journal of Solid State Circuits. January 2008.
Anantha Chandrakasan, William J. Bowhill, and Frank Fox. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press, 2000.
Jan Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits. Prentice Hall, second edition, 2003.
Neil Weste and David Harris. Principles of CMOS VLSI Design. Addison-Wesley, 2005.
