# Specifying Synchronous/Reactive Systems

The objective of developing a synchronous/reactive model is to aid in
designing real-time embedded controllers using concurrently-executing
communicating blocks.
Stephen adopts a heterogeneous approach that allows the blocks to be
specified in any language, provided their interface conforms to the model.
This allows subsystems to be written in the most suitable language,
simplifying the designer's task.
To make systems deterministic and their real-time behavior predictable,
we adopt the synchronous model of time used in the synchronous languages
Esterel, Lustre, and Argos.
Stephen applies his model to the design of reactive systems.
Reactive systems must run at the speed of their environment, and when
something happens in these systems is often as important as what happens.
For this reason, the synchronous approach has been developed, allowing
control over system timing to be as precise as control over system function.
This approach relies on the synchrony hypothesis, which assumes a system
runs infinitely fast.
This breaks time into a sequence of discrete instants and provides
global synchronization.

After reviewing the synchronous approach, Stephen Edwards presents a
new system description scheme that combines synchrony with heterogeneity.
Stephen formally present the semantics, which are complicated by the
possibility of zero-delay feedback loops, and present an efficient,
predictable execution scheme based on chaotic iteration toward a least-fixed
point solution, along with results that show it practical for
medium-sized examples.

# Synchronous Systems, Reactive Systems

Stephen Edwards considers reactive systems that are real-time
systems that process bits.
Synchronous systems have a shared notion of time and operate
under the Synchrony Hypothesis - zero-time computation (i.e., the
system runs infinitely fast).
In synchronous systems, time is an ordered sequence of instants.
In reactive systems, instants are initiated by environmental events.
Synchronous model supports deterministic concurrency.
Synchronous/reactive systems must handle simultaneous events,
feedback with zero delay, and contradiction, such as
-----------
| |
| v
O -----
/ \ \ /
/ \ \ /
----- v
^ |
| |
-----------

Here, the inverter wants to drive the lines to different values,
and the buffer wants to drive the lines to the same values.
# Time-varying behavior

Often, zero-delay feedback is not really zero delay.
At some point in the feedback path, there is delay, e.g.,
a --- b
---->| |----
| --- |
| e | v
--- | | ---
| A | --+ | B |
--- | ---
^ O |
| --- |
d -----| |<--- c
---

In this example, the enable signal `e`

either opens the
gate from Block A to Block B or from Block B to Block A but not both
at the same time.
# Fixed Point

Finding the schedule for an S/R system at a particular clock tick
amounts to finding the (least) fixed point of the system.
If `x`

is a vector of all of the output wires,
e.g. `x = [a b c d]'`

in the above example,
then the fixed point of the system would solve `f(x) = x`

,
where `f`

is a collection of the functions that map
inputs to outputs.
Using the above example,
f ( [a b c d]' ) = [a b c d]'

where ' means matrix transpose.
# Reasoning using incomplete information

A monotonic function on a complete partial order (with bottom)
has a unique least fixed point.
Handle contradiction using bottom.
The value on the wires in the previous example of contradiction
is bottom.
-----------
| |
| v
O -----
/ \ \ /
/ \ \ /
----- v
^ |
| |
-----------

The key is the use of bottom as the foundation of a complete
partial order.
Bottom represents an unspecified value.
# Monotonicity

Once a block fixes an output other than bottom, the value is fixed
and cannot change during the current clock tick.
1 ---
---> | | Bot
| + | --->
---> | |
Bot ---
0 ----
---> | \ 0
| AND | --->
---> | /
Bot ----

# Strict Functions

A strict function does not commit to an output value until all inputs
have value other than bottom.
Cycles of strict functions deadlock.
In order to work, S/R should not impose strictness on its component
functions.
# Scheduling

A student points out that in the lecture slides on SR system scheduling,
Stephen Edwards defines the border of a set of vertices as the vertices
that have output edge(s) to the set of vertices. But in his dissertation,
he defines the border of a set of vertices as the vertices that have input
edge(s) from the set of vertices.
Stephen says that both definitions are equivalent in the sense that removing
either kind of border will break strong connectivity.
He also says that finding borders is a heuristic, so using a different
definition of border might make the heuristic behave differently.
However, either should produce correct (small) schedules, and it is
unlikely that one approach would consistently produce better schedules.
# Concluding Thoughts

For S/R to work, the scheduler must be able to take partial information
and produce partial information.
If the scheduler fails to make progress, then scheduling is finished.
Once finished, any bottoms for wire values indicates a potential error.
S/R scheduling algorithms fall between *n* and *n*^{2}
where *n* is the number of outputs.
Using randomly generated graphs, the average scheduling time was
n^{5/4}.

Updated 04/18/00.