EE382C Embedded Software Systems - Codesign Projects
Hardware/Software Codesign Projects
The simultaneous design of the hardware and software components
of a system is called codesign.
Hardware/software codesign encompasses partitioning,
scheduling, synthesis, and cosimulation.
Automating codesign is not practical at the current time.
Instead, codesign techniques are used to provide guidance
to designers for making mapping decisions.
Successful approaches for design guidance limit the scope of the
For example, the codesign of dataflow graphs that can be statically
scheduled on one hardware target (e.g. FPGA) and one software target
(e.g. a digital signal processor core) has two advantages:
(1) schedules are static, and (2) mapping decisions are binary.
Below, I list information about selected hardware/software
codesign approaches to form ideas about a project.
For a project, you should tie your approach formal model or method.
If the project were related to FPGAs, then you could limit your scope
to statically schedule dataflow graphs in which you periodically change
the SDF graph, reschedule, and reconfigure the FPGA.
- Papers on codesign for dataflow graphs: look at the Ptolemy Web site and
search for 'codesign' under the
Asawaree Kalavade did her thesis on HW/SW codesign for mapping
actors in SDF graphs onto either a programmable digital signal
processor or a custom gates. Her thesis is available on-line.
- POLIS hardware/software codesign environment:
POLIS is built on top of Ptolemy using the Discrete-Event domain.
The POLIS Project is directed by Prof. Alberto Sangiovanni (UC Berkeley),
who works closely with Fiat in Italy.
- Vulcan hardware/software codesign environment
- Cadence Virtual Component Codesign
- Workshop dedicated to codesign:
NATO Advanced Study Institute Workshop on Hardware/Software Codesign.
Authors are by invitation only.
There was one in 1995, but it may be an annual workshop.
- Prof. Margarida Jacome's hardware/software codesign course,
taught each Spring semester.
- BRASS project at UC Berkeley:
Synthesis of FPGA applications using Ptolemy.
- Interesting papers on codesign with DSP cores:
- S. Pees, M. Vaupel, V. Zivojnovic, and H. Meyr,
"On core and more: a design perspective for systems-on-a-chip,"
Proc. IEEE International Conference on Applications-Specific
Systems, Architectures and Processors,
July 14-16, 1997, p. 448-457.
- V. Zivojnovic, S. Pees, C. Schlager, M. Willems, and others,
"DSP processor/compiler co-design: a quantitative approach,"
Prof. IEEE Int. Symposium on System Synthesis,
Nov. 6-8, 1996, p. 108-113.
Last updated 02/21/98.