Freescale DSP56000 Processor

Lecture by Prof. Brian L. Evans


Introduction

The DSP56000 fixed-point DSP uses 24-bit program words and 24-bit data words. It is ideal when the processing requires 17-24 bit data: It has two data paths which is useful for stereo audio processing, even though it only has one hardware multiplier unit. It takes two master clock cycles to execute one instruction cycle. Variations of the DSP56000 family include DSP56100, DSP56300, and DSP56600. The DSP56690 decodes any digital baseband communications signal.

The DSP56800 family is a hybrid DSP/microcontroller. One of the earliest applications (mid-1990s) was in speakerphones. In 2004, the DSP56800 finds applications in power control systems:

Registers

Accumulators

Features

The 56000 has the addressing of a conventional DSP processor except bit-reversed addressing. The 56000 has conditional moves to reduce branching. Here is an example of a logical inverter, where 0 is false and not zero is true:
; invert input
        clr     b       input,a          ; b = 0, a = input
        tst     a       #$01,y1          ; test a, set y1 = 1
        teq     y1,b                     ; if a = 0, then b = y1 = 1
        move    b,output                 ; output = b

References

  1. Mohamed El-Sharkaway, Digital Signal Processing Applications with Motorola's DSP56002 Processor, Prentice Hall, ISBN 0-13-569476-0, 1996.
  2. Motorola, Inc., DSP56000 Digital Signal Processing Family Manual, 1992.


Last updated 12/22/04. Send comments to (Mailbox)bevans@ece.utexas.edu