Proc. Asilomar Conference on Signals, Systems and Computers, Oct. 30-Nov. 3, 2017, Pacific Grove, CA USA.

Complex Block Floating-Point Format with Box Encoding For Wordlength Reduction in Communication Systems

Yeong F. Choo (1), Brian L. Evans (1) and Alan Gatherer (2)

(1) Department of Electrical and Computer Engineering, Wireless Networking and Communications Group, The University of Texas at Austin, Austin, TX 78712 USA
yeongfoong.choo@utexas.edu - bevans@ece.utexas.edu

(2) Huawei Technologies, Plano, Texas USA

Paper - Slides - Software

Multiantenna Communications Project

Abstract

We propose a new complex block floating-point format to reduce implementation complexity. The new format achieves wordlength reduction by sharing an exponent across the block of samples, and uses box encoding for the shared exponent to reduce quantization error. Arithmetic operations are performed on blocks of samples at time, which can also reduce implementation complexity. For a case study of a baseband quadrature amplitude modulation (QAM) transmitter and receiver, we quantify the tradeoffs in signal quality vs. implementation complexity using the new approach to represent IQ samples. Signal quality is measured using error vector magnitude (EVM) in the receiver, and implementation complexity is measured in terms of arithmetic complexity as well as memory allocation and memory input/output rates. The primary contributions of this paper are
  1. a complex block floating-point format with box encoding of the shared exponent to reduce quantization error,
  2. arithmetic operations using the new complex block floating-point format, and
  3. a QAM transceiver case study to quantify signal quality vs. implementation complexity tradeoffs using the new format and arithmetic operations.

Questions & Answers

During the presentation, audience members asked the following questions:

Q1. What is the stage of progress of this project? Is there any plans to implement or test on hardware?
A1. Simulated for error analysis and complexity requirement in MATLAB. May plan to implement or test on FPGA.

Q2. Is there any number of hardware implementation savings?
A2. I don't have any number. In their 2012 paper, Cohen & Weiss showed that it is possible to achieve 10% reduction in registers and memory footprint with a tradeoff of 10% increase in arithmetic complexity.

Q3. What is the primary motivation of the research project?
A3. Energy efficiency in cellular basestation design.

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Last Updated 11/11/17.