FloatingPoint to FixedPoint Transformation
Toolbox
Kyungtae Han and Brian L.
Evans Embedded Signal Processing
Laboratory Department of Electrical and Computer
Engineering The University of Texas at Austin, Austin, TX
787121084
05/22/06
This freely distributable toolbox automates conversion of
floatingpoint programs to fixedpoint programs and quantifies the
tradeoff in signal quality vs. implementation complexity in
fixedpoint wordlength choices. This toolbox can automatically
generate optimized fixedpoint MATLAB programs in terms of
wordlength (bit width), if floatingpoint programs and desired error
specification are given. This software can be useful to implement
digital signal processing algorithms on hardware for lower power
consumption [11] in digital signal processors (DSPs), field
programmable gate arrays (FPGAs), and applicationspecific
integrated circuits (ASICs), and for lower hardware complexity in
FPGA and ASIC.
Download
Demo
Filter design (Block design)
This demo demonstrates the automating floatingpoint to
fixedpoint transformation of a 10variable infinite impulse
response (IIR) filter. The transformation includes fixedpoint
conversion and wordlength optimization [1]. The given floatingpoint
IIR filter program ( iirfilter.m) will be converted into a fixedpoint
IIR filter program. Then, data wordlengths to optimize the signal
quality vs. implementation complexity are searched by the search
algorithm selected by the user.
 >> demo_afx
Then press 'enter' key four times. You can see search procedure.
After finishing simulation, you can see the difference between
floatingpoint output and optimized fixedpoint output in a plot. You can also find some area reduction of
optimized fixedpoint code ( iirfilter_fixed.m) in the command window. The Genetic algorithm option
provides a Pareto front ( 500th generation).
In the GA results, the horizontal axis is the signal distortion
and the vertical axis is implementation complexity (as measured
in lookup table area on an FPGA).
BPSK system design (System design)
This demo demonstrates the automating floatingpoint to
fixedpoint transformation of a 4variable BPSK system.
The transformation includes fixedpoint
conversion and wordlength optimization [1]. The given floatingpoint
BPSK system program ( bpsksystem.m) will be converted into a fixedpoint
BPSK system program. Then, data wordlengths to optimize the signal
quality (bit error rate) vs. implementation complexity are searched by the search
algorithm selected by the user.
 >> demo_afxbpsk
Select 'system', then press 'enter' key three times. You can see search procedure.
After finishing simulation, you can see some area reduction of
optimized fixedpoint code ( bpsksystem_fixed.m) in the command window. The Genetic algorithm option
provides a Pareto front ( 50th generation) and a selection to choose a particular tradeoff point on the curve
after simulations.
In the GA results, the horizontal axis is the signal distortion
and the vertical axis is implementation complexity (as measured
in lookup table area on an FPGA).
Tutorial
Gradientbased search approach Gradientbased wordlength
search algorithms utilizing gradient information can provide faster
ways to find data wordlengths but can get caught in local optima
[13].
 Open iirfilter.m and look at the given floating point program.
 >> open iirfilter
 Run a fixedpoint code generator. It generates fixedpoint
program file (iirfilter_fx.m) as well as auxiliary files.
 >> fxcodegen
 or
 >> fxcodegen('iirfilter.m')
 Select search algorithm and options, or just press 'enter' key
for default option. Setting of weight of 1 utilizes only hardware
complexity information (Local search) [4,5]. Setting of weight of
0 utilizes only error information [3]. A fraction value such as
0.5 utilizes complexity information and error information [12].
 Run wordlength optimization algorithm with input data.
 >> in = rand(1,100)
 >> iirfilter_top(in)
You can see the search results. An optimized fixedpoint file
is stored in iirfilter_fixed.m
 Open the optimized fixedpoint program
 >> open iirfilter_fixed
Optimum wordlength is embedded in the fixedpoint file. You can
replace the floating program with the automatically generated and
optimized fixedpoint program. You can also change and
add configurations for general search algorithm in config.m. This
file is copied to TOP file during code generation. Thus, after
changing configuration, code generation should be run again.
Genetic algorithm approach Wordlength search algorithms
utilizing genetic and evolutionary algorithms provide Pareto optimum
set of data wordlength to optimize the signal quality vs.
implementation complexity tradeoffs [1]. Multiple solutions for
optimum wordlength will be provided after simulation. More
information about Genetic algorithm is available in [68].
 Open iirfilter.m and look at the given floatingpoint program
 >> open iirfilter
 Run fixedpoint code generator. It generates fixedpoint
program file (iirfilter_fx.m) as well as auxiliary files.
 >> fxcodegen
 or
 >> fxcodegen('iirfilter.m')
 Select genetic algorithm.
 Run wordlength optimization algorithm with input data
 >> in = rand(1,100)
 >> iirfilter_top(in)
You can see the graphical results of 100 generations.
Simulation results are stored in iirfilter_result.mat. You can
load the result and look the Pareto Optimal set.
 >> load iirfilter_result
 >> pareto_fr
The Pareto front variable has the last generation's
Pareto optimal set with the following format [Error, Area, WL1, WL2,
WL3, ...., WL10]. (Option) You can change and add configurations for
general search algorithm in config.m. You can also change and add
configurations for Genetic algorithm in configgea.m. These files are
copied to TOP file during code generation. Thus, after changing
configuration, code generation should be run again.
Usage
 MODIFYING: Please modify your floating point program for this
software. Current version has a simple parser. Please, make your
program as simple as possible, and follow the rules below. (See
example file: iirfilter.m )
 The first line of function has an input argument for
parameter passing since wordlength is optimized according to
input data
(e.g) function out = example (in) % for block
(e.g) function error = system (gain) % for system
 The first line of function has an output argument for
parameter passing since outputs of floatingpoint and
fixedpoint will be compared for block design. For system design,
output argument should have distortion value such as bit error rate.
(e.g) function out = example (in)
(e.g) function error = system (gain) % for system
 Each line has only one arithmetic operation.
 Comment with 'fx' for desired assigned fixedpoint variable
(e.g) out = a + b; % fx (Variable 'out' is changed into
fixedpoint variable during code generation)
 Variables to be fixed point should be initialized with constants such as 0 or 1.
(e.g) acc = 0 % fx
 Array variable to be fixed point should be initialized with array constants
such as zeros or ones function.
(e.g) data = zeros(1,1000) % fx
 CODE GENERATION: Run fixedpoint code generator with your
floating point file. It generates fixedpoint program file as well
as auxiliary files.
 >> fxcodegen('yourfile.m')
Warning: The quotation marks are required. Select search
algorithm and options, or just press 'enter' key for default
option. Options are described in the other section.
 WORDLENGTH OPTIMIZATION: The generated TOP file can search
wordlength with given input data.
 (e.g.)
 >> in = rand(1,100)
 >> yourfile_top(in)
You can see the search
results. Optimized fixedpoint file is stored in yourfile_fixed.m.
The optimum wordlength is embedded in the fixedpoint file. You
can replace your floating program with the automatically generated
and optimized fixedpoint program in a system.
Option You can also change and add configurations for
general search algorithm in config.m. This file is copied to TOP
file during code generation. Thus, after changing configuration,
code generation should be run again.
 Gradientbased search algorithm
 Weight
 Search algorithm gives weight on the error or hardware
complexity for gradient information. Setting of weight of 1
utilizes only hardware complexity information. Setting of weight
of 0 utilizes only error information. A fraction value such as
0.5 utilizes both information for search direction.
 RMS error
 Root Mean Square Error of output data between floatingpoint
program and fixedpoint program.
 Genetic algorithm In configgea.m file, "...
'Termination.MaxGenerations', 50, ..." indicates maximum
generations. Please look at http://www.geatbx.com/ for more information for
GEATbx.
Hardware Complexity Model This software estimate hardware
area for FPGA. The hardware area model in [9,10] is used. You can
modify the model by changing the cost files such as cost_add.m and
cost_mul.m.
References
 K.
Han, "Fixedpoint Transformations for LowPower Embedded
Hardware and Software Design", Ph.D. dissertation ,
Electrical and Computer Engineering, The University of Texas at
Austin, August 2006.
 K. Han and B. L. Evans, "Optimum Wordlength Search Using
Sensitivity Information", EURASIP Journal on Applied Signal
Processing, special issue on Design Methods for DSP
Systems, vol. 2006, no. 5, pp. 103116, 2006.
 K. Han and B. L. Evans, "Wordlength Optimization with
ComplexityAndDistortion Measure and Its Applications to
Broadband Wireless Demodulator Design", Proc. IEEE Int. Conf. on Acoustics, Speech,
and Signal Proc., May 1721, 2004, vol. 5, pp. 3740,
Montreal, Canada.
 W. Sung and K. Kum, "Simulationbased wordlength optimization
method for fixedpoint digital signal processing systems",
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30873090, 1995.
 H. Choi and W. P. Burleson, "Searchbased wordlength
optimization for VLSI/DSP synthesis", Proc. IEEE Workshop on
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 K. S. Tang, K. F. Man, S. Kwong and Q. He, "Genetic algorithms
and their applications", IEEE Signal Processing Magazine,
vol. 13, pp. 2237, November 1996.
 C. M. Fonseca and P. J. Fleming, "Genetic algorithms for
multiobjective optimization: Formulation, discussion and
generalization", Proc. Int. Conf. Genetic Algorithm, July
1993, pp. 416423.
 D. E. Goldberg, Genetic Algorithms in Search,
Optimization, and Machine Learning, Reading, MA:
AddisonWesley, 1989.
 G. A. Constantinides, P. Y. Cheung, and W. Luk, "Wordlength
optimization for linear digital signal processing", IEEE
Trans. ComputerAided Design , vol. 22, no. 10, pp.
14321442, Oct. 2003.
 G. A. Constantinides, P. Y. Cheung, and W. Luk, "Optimum
wordlength allocation", Proc. IEEE Sym. on FieldProgrammable
Custom Computing Machines, April 2002, pp. 219228.
 K. Han, B. L. Evans, and E. E. Swartzlander, Jr., "LowPower Multipliers with Data
Wordlength Reduction", Proc. IEEE Asilomar Conf. on
Signals, Systems, and Computers, Oct. 30Nov. 2, 2005, pp.
16151619, Pacific Grove, CA USA.
Mail comments about this page to Prof. Brian L. Evans at bevans@ece.utexas.edu.
