360N: Computer Architecture

Spring 2005

University of Texas at Austin

Instructor:  Prof. Derek Chiou
Lectures: MW 5:00PM-6:30PM, ENS115
Tutorials: TH  5:00PM-6:30PM RLM7.112,   F 2:00PM-3:30PM ENS116
Unique numbers: 15620, 15625

Topics to be covered:

  • What is Architecture, Tradeoffs
  • Instruction Set Architecture, LC-3b ISA
  • Assemblers: Translating Assembly Language to ISA
  • Microarchitecture: Detailed LC-3b implementation
  • Physical memory, unaligned access, interleaving, SRAM, DRAM
  • Virtual memory, page tables, TLB, VAX model, PowerPC model, contrast with segmentation
  • Cache memory
  • Interrupts/Exceptions
  • I/O
  • Performance Improvement. Metrics, Pipelining.
  • Branch prediction
  • Out-of-order execution
  • Vector processing
  • Integer arithmetic, Floating point, IEEE Standard
  • Measurement Methodology
  • Intro to Multiprocessing, Interconnection networks, Amdahl's Law, Consistency models
  • Cache coherency
  • Alternative Models of Concurrency: SIMD, MIMD, VLIW, dataflow, etc.
  • State-of-the-art Microprocessor

Important dates:

Date

Work Issued/Due

Jan 18

Problem Set 1 Issued
(ISA, LC-3b, Assembly)

Lab 1 Issued
(write LC-3b assembler, write an assembler, assemble your program)

Jan 23

 

Jan 25

Lab 2 Issued

(Write a program in C that simulates at the instruction
cycle level the baseline LC-3b ISA. Test your simulator with
the output of the assembler for the application program
written in Programming Lab 1.)

Feb 1

Problem Set 1 Due
Problem Set 2 Issued
(Microarchitecture, physical memory, virtual memory)

Feb 6

Lab 1 Due (Feb 5 11:59pm)

Feb 8

 

Feb 13

Guest lecturer or no class (HPCA)

Lab 2 Due (Feb. 12th, 11:59PM)

Lab 3 Issued
(Finish the LC-3b)

Deadline for dropping without possible academic penalty

Feb 15

 

Feb 20

Problem Set 2 Due
Problem Set 3 Issued
(Virtual Memory, Cache Memory)

Feb 22

 

Feb 27

Lab 3 Due (Feb 26th, 11:59PM)

Lab 4 Issued
(Interrupts/Exceptions)

Mar 1

 

Mar 6

Problem Set 3 Due

Problem Set 4 Issued
(I/E, I/O)

Mar 8

EXAM 1

Mar 13

Spring break, have fun

Mar 15

Spring break, but not too much fun

Mar 20

 

Mar 22

 

Mar 27

Lab 4 Due (Mar 27 11:59pm)
Lab 5 Issued
(Virtual memory)

Last day to drop with Dean’s approval

Mar 29

Problem Set 4 Due

Problem Set 5 Issued

(OOO, integer and floating point arithmetic)

Apr 3

 

Apr 5

Problem Set 5 Due

Problem Set 6 Issued

(OOO, concurrency, multiprocessing, cache coherency)

Apr 10

 

Apr 12

 

Apr 17

Lab 5 Due (Apr 17 11:59pm)
Lab 6 Issued
(Pipelining)

Apr 19

EXAM 2

Apr 24

 

Apr 26

Problem Set 6 Due

May 1

 

May 3

Lab 6 Due (May 5 5:00pm)

May 8

 

May 10

 

May 12

TENATIVE (Registrar has power to change) FINAL EXAM TIME