EE 382V VLSI Physical Design Automation

Fall’08 – Implementation Projects

(Last updated: Oct. 1, 2008)

 

1.                eASIC Placement Contest

Please see this web site for the project description

 

http://www.cerc.utexas.edu/~ashutosh/PDClassProjectDescription.htm

 

The latest benchmark can be downloaded from here

 

ftp1.easic.com:outgoing/benchmarks_eprize1_080925.tgz

 

The ePrize announcement is here

 

http://www.easic.com/index.php?p=university

 

 

2.                 Global Routing

 

The following are the project spec for global routing.

 

Project Goal:

The goal of this project is to implement a routability-driven global router which takes ISPD98/ISPD07 benchmark as input,
and produce output in specific format. From this project, you'll learn the algorithms and its implementations
of steiner tree, maze routing and global routing.

Input Format:

ISPD98 and ISPD07 benchmarks will be given as input which has the following input format. It is available in [1].

What To Do:

Basically, you need to connect all the pins of each net under the capacity constraint, but with minimal wirelength.
The challenge here is to distribute those connections such that it satisfies the vertical/horizontal capacity as
much as possible with shorter wirelength. The final output should shows a list of routs of each net which connect
the pins of the net. You can implement the global router in C/C++ or modify the existing open source global router [1].

Output Format:

The PERL script to evaluate your solution will be provided later.

Evaluation:

The output will be evaluated in three aspects; routability, wirelength and cpu time.
The number of overflow will be used as a metric of routability, which shows excessive local routing demand.
For example, between grid (18,61) to grid (19,61) in ibm01.modified.txt, there are 14 routing resources.
-If you routing solution puts 11 routes between grid (18,61) to grid (19,61), then it means ZERO overflow.
-If you routing solution puts 14 routes between grid (18,61) to grid (19,61), then it means ZERO overflow.
-If you routing solution puts 15 routes between grid (18,61) to grid (19,61), then it means ONE overflow.
-If you routing solution puts 16 routes between grid (18,61) to grid (19,61), then it means TWO overflows.

As this project is about routability-driven global routing, the number of overflow is the most important objective.
But, you have to find good trade-off between them, as unacceptable long wirelength or cpu time will be penalized anyway.

         

Reference:

[1] http://www.ece.ucsb.edu/~kastner/labyrinth/ and http://www.ispd.cc

[2] BoxRouter2.0 (open source) http://www.cerc.utexas.edu/utda/download/BoxRouter.htm

[3] FLUTE (open source) http://class.ee.iastate.edu/cnchu/flute.html

[4] Minsik Cho and David Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP", DAC, July, 2006
[5] R. T. Hadsell and P. H. Madden, "Improved Global Routing through Congestion Estimation", DAC, June 2003.
[6] J. Westra, C. Bartels, and P. Groeneveld, "Probabilistic Congestion Prediction", ISPD, April 2004.

 


Additional Help

 

·         All the papers can be downloaded from IEEE Explorer or ACM Digital Library, directly accessible from any UT machines.  If you use your home computer, you can go to UT Library web page, http://www.lib.utexas.edu/indexes/ first, and then select the correct data base (IEEE or ACM). It will ask for your UT EID and password.  Login, you will be able to have full access to these databases. 

·         You may also be interested to find “free” CAD tools and benchmarks (even source codes) from GSRC bookshelf (http://vlsicad.eecs.umich.edu/BK/Slots/ ).

·         Check the newest ICCAD, DAC, ISPD, ISLPED papers then search backwards