EE 382V – Optimization Issues in VLSI CAD

(Fall 2009 -- Course ID: 17240)

Prof. David Z. Pan

Lecture hours and location: MW 2:00 - 3:30pm at ENS 126
Instructor contact information: email dpan at ece.utexas.edu, phone: (512) 471-1436
Office: ACES 5.434. Office hours: Tue 1-3pm, or by appointment
Course syllabus and general information as well as some useful resources and links.
Class Project Page

Course Material (tentative; please check frequently and finish reading assignment before class)

-------- Module 1: Introduction/Preliminaries -------------------------------
Lec 1 (8/26): General information and introduction

Notes set 1
Required reading:

ITRS executive summary, and design challenges (download from ITRS homepage)

Additional references:

IBM Journal of R&D on “Scaling CMOS to the limits” (Vol. 46, No 2&3, 2002): a lot of good papers from process technology to design challenges.

Lec 2 (8/31): CMOS scaling, and timing analysis/modeling issues for device and interconnect

Notes
Required reading:

Cong et al’s paper “Performance Optimization of VLSI Interconnect Layout” (sections 1 and 2)

Additional reference:

For those of you who want quick tutorial, you can read the ICCAD’97 tutorial paper

Lec 3 (9/2): More on timing/modeling issues (continued)

Notes
Required reading:

ITRS Interconnect chapter (download from ITRS homepage)

Additional reference:

Puri et al’s paper on iterative delay calculator (GLSVLSI 2002): used in IBM PDS
Weibull function (ICCAD 2002)

Sept. 7: No class due to Labor Day
Lec 4 (9/9): More on modeling issues and Project guide and discussion.
------- Module 2: Interconnect Optimization Issues
Lec 5 (9/14): Interconnect topology optimization

Notes:
Required reading:

Cong et al’s paper “Performance Optimization of VLSI Interconnect Layout” (section 3)

Lec 6 (9/16): Interconnect topology optimization (continued)

Additional reading:

Performance-Driven Interconnect Design Based on Distributed RC Delay Model, by J Cong, KS Leung, D Zhou ftp://ftp.cs.ucla.edu/tech-report/1992-reports/920043.pdf (the original A-tree paper with lots of details)

Lec 7 (9/21): Transistor/gate sizing

Notes:
Required reading:

Cong et al’s paper “Performance Optimization of VLSI Interconnect Layout” (section 4.1)
TILOS paper (ICCAD 1985): hard copy distributed in class.

Additional reading:

§ iCONTAST paper (on static sizing using convex programming) at TCAD 1993: S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, "An Exact Solution to the Transistor Sizing Problem for CMOS Circuits using Convex Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 11, pp. 1621 - 1634, November 1993.

IBM EinsTuner paper on dynamic transistor sizing: Optimization of custom MOS circuits by transistor sizing. A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah. ICCAD 1996.
Lagrangian relaxation paper by Chen et al, 1998 (ICCAD)
ICCAD 2000 Tutorial on Gain Based Synthesis by Kudva et al from IBM Research (warning: lots of slides!). You can take a look at the logic effort based gate sizing.

Lec 8 (9/23): Wire sizing with wire width planning

Notes:
Additional reference:

Cong and Leung’s classic paper on wire sizing: Optimal wiresizing under Elmore delay model, TCAD, Volume: 14 , Issue: 3 , March 1995 Pages:321 – 336
Shaping a distributed-RC line to minimize Elmore delay, Fishburn, J.P.; Schevon, C.A.; IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume: 42 , Issue: 12 , Dec. 1995 Pages:1020 – 1022 (a neat paper to read)

Lec 9 (9/28) Buffer insertion.

Notes: ICCAD’01 tutorial, ICCAD’02 slides (from Dr. Chuck Alpert at IBM ARL)
Required reading:

Van Ginneken’s classic paper on buffer insertion: “Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. Circuits Syst., May 1990, pp. 865--868.

Additional reading:

See Dr. Alpert’s slides

Lec 10 (9/30): Crosstalk noise modeling and reduction

Notes: PPT (overview), and the 2-Pi paper PPT slides.
Required reading:

2-pi model paper: " Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan (J. Cong, D.Z. Pan and P.V. Srinivas).

Additional papers:

Accurate crosstalk noise modeling for early signal integrity analysis
Li Ding; Blaauw, D.; Mazumder, P.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 22 , Issue: 5 , May 2003, Pages:627 – 634

Lec 11 (10/5): Clock synthesis

Notes: PPT
Required reading

An exact zero-skew clock routing algorithm (a classic paper) by Ren-Song Tsay, TCAD 1993 (earlier version in ICCAD 1991).
DME paper (another classic paper): Zero-skew clock routing trees with minimum wirelength, by Boese, K.D.; Kahng, A.B.; ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International , 21-25 Sept. 1992 Pages:17 - 21

Other references:

A survey paper by Eby Friedman: “Clock distribution networks in synchronous digital integrated circuits”, Friedman, E.G.; Proceedings of the IEEE , Volume: 89 , Issue: 5, May 2001 Pages:665 – 692
Cong et al’s paper “Performance Optimization of VLSI Interconnect Layout” (section 5) (very comprehensive and a lot of stuff for clock tree optimization)

Lec 12 (10/7): More on clock design under process variations (link insertion and advanced issues).

Notes: PPT
References:

Rajaram et al, DAC’04, ISPD’05, ISLPED’06, ISPD’06
Venkataraman et al, “Practical techniques to reduce skew and its variations in buffered clock networks," Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 592-596, 2005.

Lec 13 (10/12): Interconnect planning

Notes:

Interconnect Planning

Required reading:

IPEM paper: "Interconnect Performance Estimation Models for Design Planning" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001 (J. Cong and D. Z. Pan).
Buffer block planning paper: "Buffer Block Planning for Interconnect Planning and Prediction", IEEE Transactions on VLSI Systems , vol. 9, no. 6, pp.929-937, December 2001. (J. Cong, T. Kong and D. Z. Pan).

Additional resources:

J. Cong, An Interconnect-Centric Design Flow for Nanometer Technologies", Proceedings of the IEEE, vol. 89, No. 4, pp 505-528, April 2001. (a good survey on the state of the art of interconnect synthesis and planning)

Lec 14 (10/14): Interconnect planning (cont’d)

First report due
Notes:

Dr. Stroobandt’s tutorial slides on Rent’s rule for System Level Interconnect Prediction (SLIP’01).

Additional resources:

SLIP (System Level Interconnect Prediction). Please check out the web page of an international workshop dedicated to this topic. Many slides available. http://www.sliponline.org

10/19: Review for midterm and project status
10/21: Midterm
10/26: Introduction to Network-on-chips
------- Module 3: Modern Physical Synthesis in a Nutshell
10/28: Placement – a key step in nanometer design closure

Notes:

Placement

Resources:

Craftwerks: force-directed method
Gordian (quadratic programming with partition)
Capo or Feng-shui (partition-based placement): see GSRC bookshelf.
Dragon (Simulated Annealing): Dragon Website (or see GSRC bookshelf)
GSRC bookshelf. http://vlsicad.eecs.umich.edu/BK/Slots/

11/2: more on placement

The ICCAD 2007 embedded tutorial paper by Alpert, et al.

------- Module 4: Low Power and Thermal Issues
11/4: Introduction on modeling, challenges, and some key techniques

11/9: Low power

Notes

Slides set1, set 2, set 3 (new)

Reference:

ICCAD’03 tutorial on leakage: section 1, 2, 3, 4 (warning: lots of slides).
"Pushing ASIC Performance in a Power Envelope", Proc. 40th ACM/IEEE Design Automation Conference (DAC), by R. Puri et al.

11/11: More on leakage optimization and thermal issues
------- Module 5: Design for Manufacturability and Student Presentations of Selected Papers
11/16: DFM Introduction

Notes

11/18: DFM Aware Routing

Notes based on ICCAD 2007 Tutorial by David Pan

11/23: More on DFM (double patterning, etc.). ICCAD tutorial
11/25: Student presentation on selected papers

On a very recent 2009 paper – DAC, ICCAD, ISPD, etc.
Focusing on main problems and ideas!!!

11/30: Student presentation on selected papers
12/2: Student presentation on selected papers and conclusions
12/9 (Wed) ENS127 (2-5pm): final class project presentation (each team 20 minutes)

Homework/Exam and Project

Homework 1 (due 9/30)
Homework 2 (due 10/19)
Sample mid-term (spring 2006)
Class Project