EE360R – Computer Aided IC Design (Fall 2010)

Instructor: Prof. David Z. Pan

Computer-aided IC design

Email: dpan@ece.utexas.edu

Fall 2010

Office: ACES 5.434; Phone: 471-1436

Unique No. 16690

Office Hours: MW 1:30-2:30pm, or by appointment.

Lecture: MW 3:30-5:00 pm at ECJ 1.204

 

    • 9/18: Please use Discussion Forum at BB for posting questions.
    • 9/18: Please note that Lab 1 due date is extended to Oct. 4 (due to ECE-IT glitch).
    • 8/23: Welcome back to school. Note: 9/6: Labor Day

Course Outline and Schedule (tentative)

DATE

DAY

TOPIC OF LECTURE/DISCUSSION

Reading

HOMEWORK

LAB/PROJECT

EXAMS

8/25

Wed.

1. Introduction, CMOS Transistors

1.1 - 1.3

Homework 0

Lab. 1 Assigned

 

8/30

Mon.

2. CMOS Fabrication and Layout

3.1 - 3.5

 

 

 

9/1

Wed.

3. CMOS Logic

1.4 - 1.5

Homework 1

 

 

9/8

Wed.

4. MOS Transistor Theory

2.1 - 2.3.1

 

 

 

9/13

Mon.

5. DC and Transient Gate Characteristics

2.3.2 - 2.6, 4.3 - 4.4

Homework 2

 

 

9/15

Wed.

6. Logical Effort

4.5

 

 

 

9/20

Mon.

7. Combinational Circuits

9.2 - 9.2.1

Homework 3

 

 

9/22

Wed.

8. Design of Adders

11.1 - 11.2

 

 

 

9/27

Mon.

9. Datapath

11.3 - 11.10

Homework 4

 

 

9/29

Wed.

10. Interconnects in CMOS Technology

6.1 - 6.6

 

 

 

10/4

Mon.

11. Sequential Elements

10.1 - 10.4

 

  Lab. 1 Due/ Lab. 2 Assigned

 

10/6

Wed.

12. Sequential Elements (continued);

      Design Styles

Notes

 

 

 

10/11

Mon.

13. Hardware Description Languages, Synthesis

Notes

Homework 5 

 

 

10/13

Wed.

14. Memories

12.1 - 12.3

 

 

 

10/18

Mon

 

 

 

 

 Exam I;

Sample

10/20

Wed.

15. Dynamic CMOS Logic

9.2.2 - 9.2.5, 9.4 - 9.5

Homework 6 

 

 

10/25

Mon.

16. Deep Submicron Issues

2.4, 7.2

 

 

 

10/27

Wed.

17. CAMs, ROMs, PLAs

12.4 - 12.7

Homework 7 

 

 

11/1

Mon.

18. Circuit Pitfalls

9.3, 7.3

 

Lab. 2 Due/ Lab. 3 Assigned

 

11/3

Wed.

19. Introduction to Test

15, Notes

 

 

 

11/8

Mon.

Mini-review

 

 

 

 

11/10

Wed.

 

 

 

 

Exam II

Sample

11/15

Mon.

20. Packaging and I/O

13.2 - 13.3, 13.6

 

 

 

11/17

Wed.

21. Circuit Optimization

Notes

 

 

 

11/22

Mon.

22. Design for Low Power

5.1 - 5.3, 5.5

 

 

 

11/24

Wed.

23. Skew-Tolerant Design

10.5 - 10.6, 13.4

 

 

 

11/29

Mon.

24. Scaling & Economics

7.4, 14.5

 

 

 

12/1

Wed.

25. Evolution of microprocessor and SOC & Review

3.8, 4.8, 5.7, 7.8, Notes

 

 

 

12/3

Fri.

 

 

 

 Lab. 3 Due on 12/3

Final Exam time TBD