Embedded System Design and Modeling

EE382V, Unique: 17220
Semester: Fall 2009


 [1]  International Technology Roadmap for Semiconductors (ITRS), "International Technology Roadmap for Semiconductors, 2007 Edition," 2007.
 [2]  D. D. Gajski, R. H. Kuhn, "New VLSI Tools," IEEE Computer, vol. 16, no. 12, pp. 11-14, December 1983.
 [3]  L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
 [4]  K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.
 [5]  D. Gajski, J. Zhu, and R. Doemer, "Essential Issues in Codesign," Technical Report ICS-97-26, University of California, Irvine, June 1997.
 [6]  R. Doemer, "The SpecC System-Level Design Language and Methodology, Part 1," Embedded Systems Conference, March 2002.
 [7]  L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, "Models of Computation for Embedded System Design," in System-Level Synthesis, edited by A. Jerraya and J. Mermet, pp. 45-102, 1999.
 [8]  E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.
 [9]  G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.
 [10]  T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.
 [11]  E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
 [12]  D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.
 [13]  F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), June 1995.
 [14]  W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.
 [15]  R. Doemer, A. Gerstlauer, P. Kritzinger, M. Olivarez, "The SpecC System-Level Design Language and Methodology, Part 2," Embedded Systems Conference, March 2002.
 [16]  M. Olivarez, B. Bailey, "Smart Speed Technology: Results of Modeling for Embedded Applications," White Paper, Freescale Semiconductor, July 2007.
 [17]  A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.
 [18]  L. Cai, A. Gerstlauer, D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," Design Automation Conference (DAC), June 2004.
 [19]  Y. Hwang, S. Abdi, D. Gajski, "Cycle Approximate Retargetable Performance Estimation at the Transaction Level," Design, Automation and Test in Europe (DATE), March 2008.
 [20]  L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.
 [21]  R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
 [22]  A. Gerstlauer, D. Shin, S. Abdi, P. Chandraiah, D. Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)," Technical Report CECS-TR-07-05, University of California, Irvine, November 2007.
 [23]  A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.
 [24]  L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.
 [25]  B. Vanthournout, "An Insider's View on the Making of the New TLM-2.0 Standard," Open SystemC Initiative (OSCI), June 2008.
 [26]  A. Gerstlauer, H. Yu, D. Gajski, "RTOS Modeling for System-Level Design," Design, Automatin and Test in Europe (DATE), March 2003.
 [27]  G. Schirner, A. Gerstlauer, R. Doemer, "Fast and Accurate Processor Models for Efficient MPSoC Design," ACM Transaction on Design Automation of Embedded Systems (TODAES), 2009.
 [28]  A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), September 2007.

Additional references and documents are available for download on the class' Electronic Reserves page at the UT libraries.



  1. SpecC Environment Setup instructions
  2. SpecC Language Reference Manual, Version 2.0
  3. SpecC Modeling Guidelines
  4. System-On-Chip Environment (SCE) Setup instructions
  5. System-On-Chip Environment (SCE Version 2.2.0 Beta): Tutorial
  6. SCE Specification Model Reference Manual
  7. Debugging and Tracing of SpecC Designs
  8. SystemC Environment Setup instructions
  9. A SystemC Quick Reference card and a SystemC Quick Reference Guide
  10. IEEE Standard SystemC® Language Reference Manual
  11. SystemC Training from Doulos (includes a brief SystemC Tutorial)
  12. SystemC 2.0 Tutorial with emphasis on new features in Version 2.0 of the language
  13. Online SystemC Training Course from Forte Design Systems (makers of hardware synthesis tools)
  14. Another SystemC Tutorial: Part 1 and Part 2
  15. OSCI SystemC TLM-2.0 Standards
  16. TLM-2.0 in Action online video tutorial
  17. Getting Started with SystemC TLM-2.0 from Doulos


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Contents © Copyright 2009 Andreas Gerstlauer http://www.ece.utexas.edu/~gerstl/ee382v_f09