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Tutorials

  • A. Gerstlauer, "Principles: Modeling, Synthesis and Verification" in System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs, organized by Daniel D. Gajski, full-day tutorial at Design Automation and Test in Europe (DATE) Conference, Nice, France, April 2009.
  • A. Gerstlauer, "Embedded System Design: Modeling" in Concepts and Tools for Practical Embedded System Design, organized by Nikil Dutt, half-day tutorial at the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007.
  • R. Dömer, A. Gerstlauer, P. Kritzinger, M. Olivarez, "The SpecC System-Level Design Language and Methodology, Part 2," Embedded Systems Conference (ESC), San Francisco, March 2002.
  • A. Gerstlauer, "System-Level Modeling and Design: Experimentation with SpecC," in System Level Specification beyond RTL, organized by Daniel D. Gajski, half-day tutorial at Design, Automation and Test in Europe (DATE) Conference, Paris, France, March 2002.
  • A. Gerstlauer, "Modeling and Design with SpecC" and "Design of a GSM Vocoder," in SpecC Language and Design Methodology, organized by Daniel D. Gajski, half-day tutorial at Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 2001.
  • A. Gerstlauer, "Modeling and Design with SpecC," in SpecC Language and Design Methodology, organized by Daniel D. Gajski, full-day tutorial at the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2001.

Theses

  • A. Gerstlauer, Modeling Flow for Automated System Design and Exploration, Ph.D. Dissertation, Information and Computer Science, University of California, Irvine, 2004.
  • A. Gerstlauer, Entwicklung einer Zellbibliothek in CMOS und Passtransistorlogik für Low-Power-Anwendungen, Diplomarbeit, Integrierter Systementwurf, Fakultät Informatik, Universität Stuttgart, 1997 [Zusammenfassung].
    • A. Gerstlauer, Development of a Standard Cell Library in CMOS and Pass Transistor Logic for Low Power Applications, Diploma/Masters Thesis, Integrated Systems Engineering, Dept. of Computer Science, University of Stuttgart, Germany, 1997 [Abstract].
  • A. Gerstlauer, VHDL-Entwurf eines Prozessors mit RISC-Architektur, 2. Studienarbeit, Institut für Mikroelektronik Stuttgart, Universität Stuttgart, 1996.
    • A. Gerstlauer, Design of a Processor with RISC Architecture in VHDL, Institute for Microelectronics Stuttgart, University of Stuttgart, Germany, 1996 [Abstract].
  • A. Gerstlauer, Simulation verschiedener Permit-Zuweisungsverfahren in einem ATM-Zugangsnetz, 1. Studienarbeit, Institut für Nachrichtenvermittlung und Datenverarbeitung, Fakultät Elektrotechnik, Universität Stuttgart, 1994.
    • A. Gerstlauer, Simulation of Different Permit Allocation Strategies in an ATM Access Network, 1st Semester Project Thesis, Institute of Communication Networks and Computer Engineering, Dept. of Electrical Engineering, University of Stuttgart, Germany, 1994 [Abstract].

List of publications from the previous HIPERLOGIC project.