Entwicklung einer Zellbibliothek in CMOS und Passtransistorlogik für Low-Power-Andwendungen
Diplom Thesis (Diplomarbeit) No. 1483, Dept. of Computer Science, University of Stuttgart, Germany, 1997.
A European research project titled Hiperlogic (High Performance Logic) is investigating new means and methods for developing highly integrated digital circuits. The idea is to reach beyond the state of the art by combining efforts in all areas of circuit development. In addition to circuit speed, the Hiperlogic project is emphasizing on the power consumption of the circuits.
The Hiperlogic project is based on a combination of different innovations in CMOS technology. In order to make this technology available quickly, a standard static CMOS cell library has been developed in the first part of this work. Special care had to be taken on optimizing the power consumption. Eventually, the library cells were characterized for speed and power consumption.
Another aspect of the Hiperlogic project deals with new structures in high-level circuit development. Again, power consumption is one of the main concerns. Therefore, in the second part of this work a promising alternative logic family, Double Pass-Transistor Logic (DPL), was investigated. For this purpose, a cell library with basic DPL gates has been developed. Due to their special properties, the characterization of DPL cells is a difficult part. A couple of reflections were made regarding this topic.
Finally, different versions of a 32-bit carry lookahead adder were implemented using the cells of the two libraries. Using these circuit examples, both logic families were compared and judged. Under the given conditions, it turned out that standard static CMOS logic is generally superior to DPL when looking at the different aspects of circuit performance like area, speed, and power consumption.