VHDL-Entwurf eines Prozessors mit RISC-Architektur
2nd Semster Project Thesis (2. Studienarbeit), Institute for Microelectronics Stuttgart, University of Stuttgart, Germany, 1996.
In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize application specific integrated circuits (ASICs) in many designs nowadays. At the IMS this process is supported by developing and fabricating ASICs at competitive prices even in low quantities. Especially for frequently needed controlling applications, the IMS has a library of microcontroller modules. Depending on the task to be performed, a processor kernel can be integrated on one chip together with the special peripherals needed for the application.
In this work a new microcontroller kernel module was developed. Its instruction set is compatible to the microcontroller PIC17 by Microchip Technology. The processor employs a RISC architecture with separate busses for instructions and data. Instructions are 16 bit wide and the program memory has a maximum size of 64k words. The maximum size of the data memory is 256 x 8 bits. Special features include a timer/counter module and support for four interrupt sources with different priorities.
Based on the modern design methods used at the IMS the microcontroller kernel was developed using the hardware description language VHDL. First, the specification was transferred into an abstract behavioral description which was then simulated and tested. Based on that, the next step was to develop a description of the microcontroller kernel which could be automatically synthesized into a circuit. Finally, the resulting gate level netlist was again simulated and tested. In order to perform a functional test of all three description levels of the microcontroller kernel a special test program was created. At the end of the process the development results in a netlist which can be used to fabricate a chip.