Power Hour Reading Group: 2002-2003

Date
Paper
Presented By
Link
FALL 2002
09/26/02 Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, G. Semeraro, G. Magklis, R. Balasubramonian, D. Albonesi, S. Dwarkadas, and M. L. Scott, HPCA 2002 Heather Hanson hpca02.ps
10/03/02 Inherently Lower-Power High-Performance Superscalar Architectures, Zyuban, Victor and Peter M. Kogge, IEEE Trans. on Computers, March 2001 Madhavi Valluri link
10/10/02 Power: A first class design constraint. T. Mudge. Computer, vol. 34, no. 4, April 2001, pp. 52-57 Anand 
Ramachandran
mudge.pdf
10/18/02 A Static Power Model for Architects, J.A. Butts and G.S. Sohi,
 (MICRO-33), 2000.  pp. 191-201.
Adam Tate link

11/01/02
Energy Scalable System Design, Amit Sinha, Alice Wang and A. Chandrakasan IEEE Trans. on VLSI Systems April 2002
Heather Hanson

sinha.pdf
11/08/02 Managing the Impact of Increasing Microprocessor Power Consumption, Stephen Gunther, Frank Binns, Doug Carmean, Jon Hall, Intel Corp Madhavi Valluri link
11/15/02 Non-ideal Battery Properties and Low Power Operation in Wearable Computing, Thomas L. Martin, Daniel P. Siewiorek Anand
Ramachandran
link
11/22/02 Paper Rob Bell link
SPRING 2003
01/24/03 Run-time Power Estimation in High-Performance Microprocessors, Russ Joseph and Margaret Martonosi ISLPED August 2001 Tao Li rjoseph.pdf
01/31/03 A Comparison of Two Architectural Power Models, Soraya Ghiasi and Dirk Grunwald, PACS 2000 Heather Hanson pacs.pdf
02/07/03 Orion: A Power-Performance Simulator for Interconnection Networks, Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh and Sharad Malik, Micro 2002 Tao Li orion.pdf
03/05/03 Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction, , W. Zhang, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, D. Duarte and Y. Tsai, Micro 2001 Anand 
Ramachandran
micro01.pdf
03/21/03 Power-Sensitive Multithreaded Architecture, John S. Seng, Dean M. Tullsen, George Z.N. Cai, ICCD 2000 Madhavi Valluri iccd00.pdf
03/28/03 discuss Heather's research in progress Heather Hanson
04/11/03 On-Chip Decoupling Capacitor Optimization Using Architectural Level Prediction, Pant, Pant, and Willis, IEEE Transactions on VLSI, June 2002 Rob Bell on-chip.pdf
04/18/03 Energy Efficient Voltage Scheduling for Real-Time Oerating Systems, Trevor Pering and Robert Brodersen, in Proceedings of the 4th IEEE Real-Time Technology and Applications Symposium, 1998. Anand 
Ramachandran
webpage
05/02/03 DRPM: Dynamic Speed Control for Power Management in Server Class Disks , S. Gurumurthi, A. Sivasubramaniam, M. Kandemir, H. Franke. To appear in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2003. Tao Li isca03.pdf
05/9/03 Temperature-Aware Microarchitecture , Kevin Skadron, Mircea R. Stan, Wei Huang,Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan. Proceedings of the International Symposium on Computer Architecture (ISCA), June 2003. Heather Hanson hotspot.html
05/16/03 Vertigo: Automatic Performance-Setting for Linux , Kristzian Flautner, Trevor Mudge. OSDI02. Sriram Sambamurthy osdi02.pdf
SUMMER 2003
06/13/03 Vertigo: Automatic Performance-Setting for Linux, Discussion Part II
, Kristzian Flautner, Trevor Mudge. OSDI02.
Sriram Sambamurthy osdi02.pdf
06/20/03 System Approaches to Power Management (PowerWise)
Dennis Monticelli, National Semiconductor
Sriram & Heather whitepaper
07/02/03 Reducing Power Density through Activity Migration Seongmoo Heo, Kenneth Barr, Krste Asanovic.
Madhavi Valluri actmig03.pdf
07/11/03 Automatic performance setting for dynamic voltage scaling.
K. Flautner, S. Reinhardt, and T. Mudge. ACM Journal of Wireless Networks, vol. 8, no. 5, Sep. 2002, pp. 507-520.
Anand Ramachandran mobicom01.pdf
08/05/03 Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction, Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor Mudge, Micro 2002 CK Kim drowsy.pdf