Joon-Sung Yang

Ph.D.
Computer Engineering Research Center
University of Texas at Austin


CATLAB

[Contacts]

(office)	ACES 6SEo2D
(email)	js21.yang@gmail.com
(cell)	512-786-5218

Biography

Joon-Sung Yang completed his Ph.D. in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He joined UT Austin in Fall, 2005. He received his M.S degree at UT Austin in 2007 and B.S. degree from Yonsei University, Seoul, Korea in 2003. His research interests are in VLSI testing focusing on Design For Debug (DFD) and Design For Testability (DFT). He worked in the Computer Aided Testing (CAT) Lab under Prof. Nur Touba.

Education

• Ph.D. - Electrical and Computer Engineering, University of Texas at Austin, Aug, 2009
  • Disseration : Enhancing Silcion Debug Techniques vis DFD Hardware Insertion
• M.S. - Electrical and Computer Engineering, University of Texas at Austin, 2007
  • Thesis : Expanding trace buffer observation window for in-system silicon debug through selective capture
• B.S. - Electrical Engineering, Yonsei University, 2003
  • Thesis : 16bit RISC Machine Implementation

Research Interests

• DFD (Design For Debug)
• DFT (Design For Testability)
• Test Data Compression

Publications

• J.-S. Yang, B. Nadeau-Dostie and N.A. Touba, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points", Proc. of IEEE Symposium on Defect and Fault Tolerance, 2009.

• J.-S. Yang, B. Nadeau-Dostie and N.A. Touba, "Test Point Inserting Using Functional Flip-Flops to Drive Control Points", Proc. of IEEE International Test Conference, 2009.

• J.-S. Yang, N.A. Touba, S.-Y. Yang and T.M. Mak "An Industrial Case Study for X-Canceling MISR", Proc. of IEEE International Test Conference, 2009.

• J.-S. Yang and N.A. Touba, "Automated Selection of Signals to Observe for Efficient Silicon Debug", Proc. of IEEE VLSI Test Symposium, 2009.

• J.-S. Yang and N.A. Touba, "Enhancing Silicon Debug via Periodic Monitoring", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 125-133, 2008. (Received Best Paper Award)

• J.-S. Yang and N.A. Touba, "Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture", Proc. of IEEE VLSI Test Symposium, pp. 345-351, 2008.

• J.-S. Yang, A. Rajaram, N. Shi, J. Chen and D.Z. Pan , "Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis", International Symposium on Quality Electronic Design, pp. 398-403, 2007.

Presentations

• "Selection Signals to Observe for Silicon Debug", IEEE International Test Synthesis Workshop, Mar. 2009.
• "Expanding Observation Window for Trace Buffer vis Selective Data Capture", IEEE International Test Synthesis Workshop, Apr. 2008.
• "Expanding Trace Buffer Observation Window using Two Dimensional Compaction", IEEE Latin-American Test Workshop, Feb. 2008.

Work Experience

• Intel, AZ (Sep. 2009 - Present)
  • Test R&D Engeineer at LSTD(Logic and System Test Development) Group
  • Research on High Volume Functional Testing
  • Path Finding

• Intel, OR - Internship (Jun. 2008 - Aug. 2008)
  • Internship at ATTM(Advanced Test Technology and Method) Group
  • Evaluation of X-Canceling Technology with Intel Chipset and Microprocessor Designs
  • Analysis on Test Coverage, DFT Logic Cost and Test Time with X-Canceling Schemes

• Qualcomm, CA - Internship (May. 2007 - Aug. 2007)
  • Internship at DFT Design Group
  • Fault Grading, ATPG and JTAG Regression

• Samsung Electronics, Korea (Aug. 2003 - Jul. 2005)
  • Assistant Engineer at Flash Memory Design Group
  • Designed 73nm 4Gb SLC and 63nm 8Gb MLC NAND Type Flash Memories
  • Timing Analysis, Post Layout Simulation, Noise Analysis and Layout

Resume

• Resume Link - Resume

Personal

• Picture Link - Picasa Web Album
• Friends Link -
  • Rudrajit Datta