Kevin J. Nowka
received his B.S. degree in computer engineering from Iowa State University in
1986 and his M.S. and Ph.D. degrees in electrical engineering from Stanford
University in 1988 and 1995, respectively.
He joined the IBM Austin Research Laboratory in 1996 where he has
conducted research on CMOS VLSI circuits and arithmetic functions for
application to the design of high-frequency and low-power CMOS processors. He
developed circuits for two one-gigahertz microprocessors and for an ultra
low-power embedded PowerPC processor.
H. Peter Hofstee
holds a Drs. degree in theoretical physics from Groningen University in the Netherlands, and MS and PhD
degrees in computer science from the California Institute of Technology. He is
interested in concurrent systems in general and in high-performance
microprocessor design in particular. From '95 to '01 he worked in the IBM
Austin Research Laboratory on high-performance microprocessor prototypes
including the first 1GHz CMOS microprocessor in '98. He has consulted
extensively for the IBM server division on future microprocessor designs. He is
currently microprocessor architect in the newly formed "Cell" design
center, a collaboration between Sony, Toshiba and IBM.
Byron Krauter received the B.S. degree in physics and mathematics
and the M.S. degree in electrical engineering from the University of Nebraska,
Lincoln, in 1976 and 1978, respectively.
He received the Ph.D. degree in electrical engineering from the
University of Texas, Austin, in 1995.He has
been with IBM since 1979 and is presently working in a VLSI CAD tools
development group in Austin, TX. His
research interests include sparse boundary element method (BEM) techniques for
inductance and capacitance extraction and on-chip interconnect analysis.
Héctor Sánchez
Héctor Sánchez is a native of San Juan, Puerto Rico. He is the Chief Engineer in charge of the Advanced Circuits Design Center (AC/DC) of the Networking and Computing Systems Group of the Motorola Semiconductor Products Sector, a group dedicated to the development of PLL, I/O, and future technology. Over the last 13 years he has worked as a custom circuit designer with Motorola's Semiconductor Products Sector in Austin, Texas working on the development of PowerPC microprocessors. He received a BS and ME degrees in electrical engineering from Texas A&M University in 1987 and 1990, respectively. His professional activities include: phase-locked loop circuit design, clock generation, clock distribution, high-speed analog-digital circuits, design for low-power, microprocessor thermal management, temperature sensor circuit design, I/O buffer design, microprocessor chip integration, and technology definition for sub-100nm technologies. He has authored more than 17 papers and has 8 patents granted and several pending. He is a member of the Digital sub-committee at the IEEE ISSCC (2001-2004) and a member of the IEEE International SOI Conference Committee ( 2002-2004). He is a member of IEEE.
Steve
Sullivan has over 20 years of experience and holds 6 patents in the area of
high-performance memory circuit design. He is currently working on a next
generation microprocessor with Intel Corporation and has contributed to
Motorola's 68K, PowerPC 604 and "G4" processors. Prior to that, Steve has worked
with Digital Equipment Corporation and IBM on their embedded SRAM arrays. Steve
received a Bachelors of Electrical Engineering from Manhattan College and a
Masters in Electrical Engineering from Polytechnic Institute of N.Y.
Matt Amatangelo holds BSEE and MSEE degrees from the University of Pittsburgh and the University of Central Florida, respectively. Matt is currently at Intel in capacity of tools methodology development. He has been involved with global and transistor-level timing and timing tool development for the passed eleven years at AMD, Sun, and IBM. His work prior to that consisted of custom circuit design, ASIC design, and device engineering and responsibilities included project leadership for image and signal processor ICs. He has worked for semiconductor companies and in the defense industry. He has published papers pertaining to computer architecture and design methodology, was an IEEE computer architecture panel member, instructed internal company courses in CMOS and VLSI design, was invited to lecture at UCLA's VLSI Design course, and holds patents in circuit/logic design and tool algorithms.
Gian
Gerosa has 24 years experience in the semiconductor industry since obtaining
his PhD in electrical engineering from the Ohio State University (OSU) in 1982.
He has a BSEE from the Georgia Institute of Technology (1977) and a MSEE from
OSU (1980). He started his career at Intel Corporation as a device engineer
working on 1.2um CMOS technology development (1982-1985). He moved on to
circuit design related activities on various memory product projects (non-volatile,
DRAM, SRAM) while at MOTOROLA (1985-1990). In the 90’s, Gian was involved in
the design of a cache controller (1990-1991) with chip integration and clocking
responsibilities. In 1992, Gian was a team member involved in the formation of
the joint IBM/MOTOROLA SOMERSET design center to develop POWERPC RISC
microprocessors. From 1992-1994, he led the PowerPC603 integration team where
he was responsible for integration, PLL design, clocking, I/O buffer design,
ESD protection, and stdcell/data path library design.
During 1994 through 1997, he took the role of design manager for the PowerPC750
RISC microprocessor development and production ramp. In 1998, he started a next
generation RISC microprocessor design. He re-joined Intel in early 1999 to
co-lead a new ia32 microprocessor design in 100nm CMOS technology; from 1999
through 2000, he ramped the design team in Austin,
Texas while participating in technology/design team development
activities.
Gian is currently
focused on overall project circuit issues to insure a successful volume ramp
into the next generation CMOS technology (65nm). Gian has 10 issued patents and
1 pending all in the area of circuit design and ESD protection schemes. He has
contributed to over 18 refereed papers related to chip design, circuit design,
and ESD protection; 2 of these are full-length journal papers on the PowerPC
603 and PowerPC 750 RISC microprocessors (JSSC94 and JSSC97). Gian was a member
of the ISSCC digital sub-committee (1997-1999) where he chaired or co-chaired
several clocking/logic sessions and was the 1998 JSSC guest editor. Gian is an
IEEE member.
Mark
McDermott has 33 years of experience in
product development of large silicon system.
Mark is currently a Research Fellow in the ECE Department at the
Univ. of Texas. Prior to this he was VP of Engineering at Coherent Logix, CEO of DynaFlow Computing, Inc., VP Engineering
at Somerset Embedded Technologies, Inc., VP Engineering at VisionFlow, Inc.,
General Manager and Director of the Texas Development Center for Intel
Corporation, Director of the PowerPC Somerset Design Center and Director of the
Austin Design Center for Cyrix, Inc. Mark co-founded Logical Silicon Solutions,
Inc. in 1990, Accelerated Solutions Corp. in 1984 and MonoCom
Systems, Inc. in 1981. Previous hardware
and software design experience includes: low-power CMOS microprocessors, speech
synthesizers, BiCMOS cache controllers, logic simulation hardware accelerators, micro-coded bit-slice processors, traffic
controllers, industrial controllers and communication controllers.
His current interests
include research on how to improve design and verification productivity in
today’s silicon system designs. He is an Adjunct Assistant Professor in ECE
Department at the University of Texas where he teaches graduate level courses
in silicon system design and technical entrepreneurship. He is on the technical advisory boards for three
design tool companies: Obsidian Software Inc., Nascentric, Inc., and Pyxis,
Inc.
Mark received a
Bachelors degree in Electrical Engineering from the University of New Mexico
and a Masters in Electrical Engineering from the University of Texas. Mark is a registered professional engineer
and a member of the IEEE, ACM and NSPE/TSPE.
He has 19 patents and a number of publications in the areas of IC design and
engineering management.