Spring 2006: VLSI-2
EE 382M-8
Unique: 15910
Class meets on Thursday: 6:30 - 9:30
Room: ENS 127
Course Goals:
This
course is intended to provide the student with the basic capability to design,
analyze, characterize and optimize transistor level circuits. Current VLSI
issues such as noise analysis, power delivery, power management, timing
analysis, clocking, floor-planning/integration, and transistor/wire scaling
will be covered. Circuit designers from IBM, AMD, SUN, Intel and FreeScale will
teach the course. The material presented in the course will be as close to
state of the art as possible. There will be 4 major homework assignments and a
class project.
Student
must have already taken the EE382M VLSI-I course and have background in logic
and basic circuit design, with a working knowledge of EDA tools –
specifically HSPICE. A basic understanding of microprocessor architecture is
required to complete the class project.
Gian Gerosa Intel
Peter Hofstee IBM
Robert Montoye IBM
Kevin Nowka IBM
Byron Krauter IBM
Matthew Amatangelo SUN Microsystems
Hector Sanchez Freescale
Steve Sullivan Intel
J
Mark McDermott
Office: ENS 425
Phone: 471-3253
Office hours: By appointment
Other office hours by appointment
Chandrakasan,
Bowhill, Fox, Design of High-Performance Microprocessor Circuits, IEEE
Press, 2000.
Bernstein,
et al., High Speed CMOS Design Styles, Kluwer Academic
Harris, Skew
Tolerant Circuit Design, Morgan Kaufmann Publishers
Weste
& Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective
(second edition), Addison Wesley
V.
G. Oklobdzija, The Computer Engineering Handbook, CRC Press, Boca Raton,
Florida, 2002.
Computer Lab:
The computer lab is located in the ENS Learning Resources Center, 5th
floor.
EDA tools:
You will
need to read the following HSPICE references to complete the homework and
project:
Digital
Circuit Simulation using HSPICE
Yet
another tutorial on HSPICE
If you
are really interested, here is a 1934 page description about HSPICE
This project assignment will be given out during first week of class to provide plenty of time to complete it. Project is due May 5th. The class will be assigned to teams to do the various components of the design. The intent of the project is to do a top-down design of an embedded SOC. The OR1200 processor will be used as the processor core for this project.
Link
to Class Project Directory
|
Dates
(Thursday) |
|
Lecture Topic |
Instructor |
Lecture Notes
1 per page |
Lecture Notes
4 per page |
HW Assignments |
Jan 19 |
1
|
Introduction to VLSI-II
Class Project Overview |
McDermott |
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2 |
Transistor and Process Technology |
Gerosa |
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Jan 26 |
3 |
Optimal fanout, logical effort, and
sizing |
McDermott |
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4 |
Early Design Floor Planning |
McDermott |
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Feb 2 |
5 |
Flip-flop design |
Gerosa |
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6 |
Array Design for EDP |
Sullivan |
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Feb 9 |
7 |
DSM Interconnect |
Moench |
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8 |
Basic Timing Analysis |
Amatangelo |
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Feb 16 |
9 |
Power Delivery |
Krauter |
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10 |
Global Clocking |
|
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Feb 23 |
11 |
DFT, DFD, DFX |
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12 |
Domino Circuit Design |
Nowka |
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Mar 2 |
13 |
|
McDermott |
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Exam #1 |
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Mar 9 |
14 |
Noise |
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15 |
Deep Pipelined Design |
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Mar 13-19 |
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SPRING BREAK |
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Mar 23 |
16 |
Array Circuit Design |
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17 |
Advanced Timing Analysis |
Amatangelo |
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Mar 30 |
18 |
Arch Design for Low Power |
Nowka |
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19 |
Circuit Design for Low Power |
Hofstee |
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Apr 6 |
20 |
|
McDermott |
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21 |
I/O, ESD |
Krauter |
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Apr 13 |
22 |
Asynchronous Design |
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Exam #2 |
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Apr 20 |
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All |
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Apr 27 |
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All |
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May 4 |
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All |
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Homework: 40%
Exam 1: 15%
Exam 2: 15%
Class Project: 30% (graded as a
class)
Penalties:
Penalty for late submission of
homework and class project:
25% per working day. (Maximum: 100%).
Homework is due at the
beginning of class on the due date.
© Copyright 2001, 2002, 2003, 2004, 2005 Mark McDermott
Web page maintained by RTM @
zoinky.com