Fall 2008

EE 382M-8  Unique: 17215

VLSI-2

NOTE: ECD Only - no auditors

 

 

Course Goals:

This course is intended to provide the student with the two basic capabilities: 1) To do the early design planning for an embedded SOC using a high level RTL model and 2) To do the circuit feasibility analysis of the critical components of the SOC. Current VLSI issues such as noise analysis, power delivery, power management, timing analysis, clocking, floor-planning/integration, and transistor/wire scaling will be covered. Circuit designers from IBM, Centaur, Intrinsity, Intel, Texas Instruments and FreeScale will co-teach the course. The material presented in the course will be as close to state of the art as possible. There will be 4 major homework assignments and a class project. The homework assignments focus on circuit feasibility analysis and the project focuses on the early design planning.

 

Course prerequisites: 

Student must have already taken the EE382M VLSI-I course and have background in basic logic and circuit design, with a working knowledge of EDA tools – specifically HSPICE, Synopsys Design Compiler and Verilog. A basic understanding of microprocessor architecture is mandatory to complete the class project.

 

Class Project

 

This class project assignment will be given out during first day of class to provide plenty of time to complete it (the project takes all semester to complete and is a lot of work). Project is due Dec 11th. The class will be assigned to teams to do the various components of the design. The intent of the project is to do the early design planning of an embedded SOC. The OR1200 processor core and various peripherals will be used for this project.

 

Class Project Details

 

Link to Student Maintained Class Project Directory

 

OR1200 Overview

 

 

 

Instructors:

Gian Gerosa  Intel

Steven Sullivan Intrinsity

Peter Hofstee IBM

Kevin Nowka IBM

Byron Krauter IBM

Matthew Amatangelo Intel

Hector Sanchez Freescale

Jerry Moench Centaur

Romi Datta Texas Instruments

Mark McDermott
Office: ENS 425

Phone: 471-3253
Office hours: Thursday 5:30-6:30PM or by Appointment

Instructor Biographies

 

TAs

 

Course outline and schedule

 

 

Dates	Time	Lecture Topic	Instructor	Lecture Notes	HW Assignments
Aug 22	8:00 - 8:30	Introduction & Class Project Overview	Sullivan	Intro Lecture 1	HW #1   Due Sept 30th
	8:30 - 9:15	Early Design Planning (EDP):  Front End	Sullivan	Lecture 2
	9:15 - 10:15	Early Design Planning: Back End	Sullivan	Lecture 3
	10:30 - 12:00	Basic Timing Analysis for EDP	Amatangelo	Lecture 4a Lecture 4b
Aug 23	8:00 – 9:15	Transistor and Process Technology	Gerosa	Lecture 5
	9:15 – 10:30	Flip-flop design	Gerosa	Lecture 6
	10:45 – 12:00	Memory Array Design for EDP	Sullivan	Lecture 7
Sep 19	8:00 – 9:15	Global Clocking	Sanchez	Lecture 8	HW #2   Due Oct 30th
	9:15 – 10:30	DSM Interconnect	Moench	Lecture 12
	10:45 – 12:00	Array Circuit Design	Sullivan	Lecture 11
Sep 20	8:00 – 9:15	Variable Aware Design	Amatangelo	Lecture 9
	9:15 – 10:30	Static & Statistical Timing Analysis	Amatangelo	Lecture 10
	10:45 – 12:00	Project Update	Sullivan
Oct 17	8:00 – 9:15	Exam #1	Sullivan	Sample Exam	HW #3   Due Dec 1st
	9:15 – 10:30	Noise Analysis	Krauter	Lecture 14
	10:45 – 12:00	Power Delivery & Management	Krauter	Lecture 15
Oct 18	8:00 – 9:15	Project Update	Sullivan
	9:15 – 10:30	Deep Pipelined Design	Romi Datta	Lecture 16
	10:45 – 12:00	DFT, DFD, DFX	Sullivan	Lecture 17
Nov 14	8:00 – 9:15	Arch Design for Low Power	Hofstee	Lecture 18
	9:15 – 10:30	Asynchronous Design	Hofstee	Lecture 20
	10:45 – 12:00	Project Update	Sullivan
Nov 15	8:00 – 9:15	I/O, ESD	Krauter	Lecture 21
	9:15 – 10:30	Circuit Design for Low Power	Nowka	Lecture 19
	10:45 – 12:00	Exam #2	Sullivan
Dec 11	1:00 - 5:00	Class Project Reviews
Dec 12	1:00 - 5:00	Class Project Reviews

 

 

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Reference Books:

Chandrakasan, Bowhill, Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2000.

Bernstein, et al., High Speed CMOS Design Styles, Kluwer Academic

Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publishers

Weste & Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective (second edition), Addison Wesley

V. G. Oklobdzija, The Computer Engineering Handbook, CRC Press, Boca Raton, Florida, 2002.

 

Various articles

 

 

 

Computer Lab:

 

The computer lab is located in the ENS Learning Resources Center, 5th floor.

 

 

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Grading:

Homework: 40%

Exam I: 15%

Exam 2: 15%

Class Project: 30%

 

Penalties:

Penalty for late submission of homework and class project:
25% per working day. (Maximum: 100%).

 

 

© Copyright 2001 - 2008 Mark McDermott