VLSI Course

Spring 2009: VLSI-2

EE 382M-8

Unique: tbd

Class meets on Thursday: 18:30 - 21:15

Room: ENS 127

Auditors Welcome

Course Goals:

This course is intended to provide the student with the two basic capabilities: 1) To do the early design planning for an embedded SOC using a high level RTL model and 2) To do the circuit feasibility analysis of the critical components of the SOC. Current VLSI issues such as noise analysis, power delivery, power management, timing analysis, clocking, floor-planning/integration, and transistor/wire scaling will be covered. Circuit designers from IBM, AMD, Centaur, Intrinsity, Intel and FreeScale will co-teach the course. The material presented in the course will be as close to state of the art as possible. There will be 4 major homework assignments and a class project. The homework assignments focus on circuit feasibility analysis and the project focuses on the early design planning.

Course prerequisites:

Student must have already taken the EE382M VLSI-I course and have background in basic logic and circuit design, with a working knowledge of EDA tools – specifically HSPICE, Synopsys Design Compiler and Verilog. A basic understanding of microprocessor architecture is mandatory to complete the class project.

REQUISITE WARNING: This course is requires a lot of work to complete. If you don't have the time to put in on the course you should take another class.

Instructors:

Gian Gerosa Intel

Steven Sullivan Intrinsity

Peter Hofstee IBM

Kevin Nowka IBM

Byron Krauter IBM

Matthew Amatangelo Intel

Hector Sanchez Freescale

Jerry Moench Centaur

Romi Datta Texas Instruments

Mark McDermott
Office: ENS 425

Phone: 471-3253
Office hours: Thursday 5:30-6:30PM or by Appointment

Instructor Biographies

Class TA

TBD

Office: LRC 5th Floor

Hours: TBD

email: vlsi2-ta at ece.utexas.edu

Class Project

This class project assignment will be given out during first day of class to provide plenty of time to complete it (the project takes all semester to complete and is a lot of work). Project is due May 7th. The class will be assigned to teams to do the various components of the design. The intent of the project is to do the early design planning of an embedded processor core. The SUN Niagara processor core will be used for this project.

Class Project Details

Link to Student Maintained Class Project Directory

SUN Niagara Overview

Course outline and schedule:

Dates (Thursday)	Lecture #	Lecture Topic	Instructor	Lecture Notes	HW Assignments
Jan 22	1	Introduction to VLSI-II Class Project Overview	McDermott	Lecture 0 Lecture 1	HW #1
Jan 22	2	Transistor and Process Technology	Gerosa	Lecture 2
Jan 29	3	Early Design Planning: Front End	McDermott	Lecture 3
Jan 29	4	Early Design Planning: Back End	McDermott	Lecture 4
Feb 5	5	Flip-flop design	Gerosa	Lecture 5	HW #2
Feb 5	6	Timing Analysis for EDP	Amatangelo	Lecture 6a Lecture 6b
Feb 12	7	Global Clocking	Sanchez	Lecture 7
Feb 12	8	Array Design for EDP	Sullivan	Lecture 8
Feb 19	9	Variable Aware Circuit Design	McDermott	Lecture 9
Feb 19	10	Static and Statistical Timing Analysis	Amatangelo	Lecture 10
Feb 26	11	Power Delivery & Management	Krauter	Lecture 11	HW #3
Feb 26	12	DSM Interconnect	Moench	Lecture 12
Mar5	13	Dynamic Circuits	McDermott	Lecture 13
Mar5		Exam #1	McDermott
Mar 12	14	Array Circuit Design	Sullivan	Lecture 14
Mar 12		Mid-Semester Project Status Review	McDermott
Mar 16-21		SPRING BREAK
Mar 26	16	I/O ESD	Krauter	Lecture 15	HW #4
Mar 26	17	Signal Integrity	Krauter	Lecture 16
Apr 2	18	DFT, DFD, DFX	Datta	Lecture 18
Apr 2	19	Deep Pipelined Design	Datta	Lecture 19
Apr 9	20	Arch Design for Low Power	Hofstee	Lecture 20
Apr 9	21	Circuit Design for Low Power	Nowka	Lecture 21
Apr 16	22	Asynchronous Design	Hofstee	Lecture 22
Apr 16		Exam #2	McDermott
Apr 23		Class Project Reviews	All
Apr 30		Class Project Reviews	All
May 7		Class Project Reviews	All