Spring 2017

EE 382M.8: VLSI-2 

Classroom: UTA 7.532

 


Course Goals:
 

This course is intended to provide the student with the two basic capabilities:

1) To do the early design planning for an embedded SOC using a high level RTL model.

2) To do the circuit feasibility analysis of the critical components of an SOC.

Current VLSI issues such as noise analysis, power delivery, power management, timing analysis, clocking, floor-planning/integration, and transistor/wire scaling will be covered. Circuit designers from Intel, TSMC, and Everspin Technologies will co-teach the course. The material presented in the course will be as close to state of the art as possible.

There will be 3 major homework assignments, a class project, a mid-Semester Exam and a Final Exam. The homework assignments focus on circuit feasibility analysis. The project focuses on the early design planning, synthesis, place and route of an SOC.


Course Prerequisites:
 

Student must have already taken the EE382M VLSI-I course and have a background in basic logic and circuit design, with a working knowledge of EDA tools -- specifically HSPICE, Synopsys Design Compiler and Verilog. A basic understanding of microprocessor architecture is mandatory to complete the class project.


Class Project:
 

This class project assignment will be given out during first day of class to provide plenty of time to complete it (the project takes all semester to complete and is a lot of work). There will be midterm project review on March 7th, and the final project design reviews are on May 2. The project report is due May 5. Class attendees will be assigned to teams to do the various components of the design, subject to constraints on area, performance and power. The project focuses on the early design planning of an embedded SOC. An ARM V2 processor core and various peripherals will be used for this project.

Class Project Details


Instructors:

Mark McDermott
Office: UTA 7.220, Phone: (512) 471-3253
Office hours: Tue 5:00 - 6:00 pm, or by appointment

E-Mail:

 

Jacob Abraham    

E-mail:

 

Gian Gerosa  

E-mail:

 

Alan Drake

TSMC   

E-mail:

 

Syed M. Alam

Everspin Technologies   

E-mail:


TA:
 

Wuxi Li
Office:  AHG 122
Hours Mon/Wed 16:00 - 17:30

E-mail:


Course outline and schedule:

Week Date Day Time

Lecture Topic

Instructor LECTURE # Homework
1 Jan. 17 Tue 6:30 - 7:45pm Introduction & Class Project Overview McDermott 1  
1 Jan. 17 Tue 8:00 - 9:15pm Transistor and Process Technology McDermott 2

Deliver HW #1

2 Jan. 24 Tue 6:30 - 7:45pm EDP: Front End McDermott 3  
2 Jan. 24 Tue 8:00 - 9:15pm EDP: Timing Analysis McDermott 4  
3 Jan 31 Tue 6:30 - 7:45pm EDP: Back End incl. Memories McDermott 5  
3 Jan 31 Tue 8:00 - 9:15pm  Overview of Process and Design Variation McDermott 6  
4 Feb. 7 Tue 6:30 - 7:45pm Static Timing Analysis (STA) McDermott 7  
4 Feb. 7 Tue 8:00 - 9:15pm  Statistical STA + PRIMETIME review McDermott 8  
5 Feb. 14 Tue 6:30 - 7:45pm Flip-flop design Gerosa 9

Deliver HW #2

5 Feb. 14 Tue 8:00 - 9:15pm CMOS Level Shifters, FLOP-based dividers Gerosa 10

Collect HW #1

6 Feb. 21 Tue 6:30 - 7:45pm Design for Testability Abraham 11  
6 Feb. 21 Tue 8:00 - 9:15pm Clocking McDermott 12  
7 Feb 28 Tue 6:30 - 7:45pm Variability Aware Circuit Design Drake 13  
7 Feb 28 Tue 8:00 - 9:15pm Low Power Circuit Design Drake 14  
8 Mar. 7 Tue 6:30 - 10:00pm Mid-Semester Project Review    

Deliver HW # 3

9      

SPRING BREAK (Mar 14 - 19)

     
10

Mar. 21

Tue

6:30 - 10:00pm

Mid-Semester EXAM: Based on Lectures 2-14

   

Collect HW #2

11   Mar 28 Tue 6:30 - 7:45pm Noise Analysis McDermott 15  
11   Mar 28 Tue 8:00 - 9:15pm Array Circuit Design McDermott 16  
12 Apr 4 Tue 6:30 - 7:45pm IO Design McDermott 17  
12 Apr 4 Tue 8:00 - 9:15pm Interconnect & Fabrics McDermott 18  
13 Apr 11 Tue 6:30 - 7:45pm Non-Volatile Memories 1 Alam 19

Collect HW #3

13 Apr 11 Tue 8:00 - 9:15pm Non-Volatile Memories 2 Alam 20  
14 Apr 18 Tue 6:30 - 7:45pm Power Gating 1 McDermott 21  
14 Apr 18 Tue 8:00 - 9:15pm  Power Gating 2 McDermott 22  
15 Apr 25 Tue 6:30 - 9:00pm Final Project Reviews      
16 May 2 Tue 6:30 - 9:00pm      


Reference Books:
 

Chandrakasan, Bowhill, Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2000.

Bernstein, et al., High Speed CMOS Design Styles, Kluwer Academic Publishers

Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publishers

Weste & Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective (second edition), Addison Wesley

V. G. Oklobdzija, The Computer Engineering Handbook, CRC Press, Boca Raton, Florida, 2002.


Grading:

Homework: 15%

Mid-Semester Exam 1: 20%

Final Exam: 25%

Class Project: 40%

 

Penalties:

 
Penalty for late submission of homework and class project: 25% per working day (Maximum: 100%)

 

Academic dishonesty:

 
Oral discussion of homework problems is encouraged. However, be sure to submit your own individual and independent solution. Labs and final projects can be done in teams. Collaboration on projects is encouraged. Copying of any part of a homework/lab solution or project report without explicit reference to its source is plagiarism and considered cheating.

 


Electronic Mail Notification Policy:

In this course e-mail will be used as a means of communication with students. You will be responsible for checking your e-mail regularly for class work and announcements. The complete text of the University electronic mail notification policy and instructions for updating your e-mail address are available at http://www.utexas.edu/its/policies/emailnotify.html


Use of Canvas and Class Web Site

This course uses the class web page and Canvas to distribute course materials, to communicate and collaborate online, to submit assignments and to post solutions and grades. You will be responsible for checking the class web page and the Canvas course site regularly for class work and announcements. As with all computer systems, there are occasional scheduled downtimes as well as unanticipated disruptions. Notification of disruptions will be posted on the Canvas login page. Scheduled downtimes are not an excuse for late work. However, if there is an unscheduled downtime for a significant period of time, I will make an adjustment if it occurs close to the due date.


Students with disabilities

The University of Texas at Austin provides upon request appropriate academic accommodations for qualified students with disabilities. For more information, contact the Services for Students with Disabilities (SSD) at 471-6259, http://ddce.utexas.edu/disability/.


Religious Holidays

Religious holy days sometimes conflict with class and examination schedules. If you miss an examination, work assignment, or other project due to the observance of a religious holy day you will be given an opportunity to complete the work missed within a reasonable time after the absence. It is the policy of The University of Texas at Austin that you must notify each of your instructors at least fourteen days prior to the classes scheduled on dates you will be absent to observe a religious holy day.


Classroom Evacuation and Emergency Preparedness

All occupants of university buildings are required to evacuate a building when a fire alarm and/ or an official announcement is made indicating a potentially dangerous situation within the building. Familiarize yourself with all exit doors of each classroom and building you may occupy. Remember that the nearest exit door may not be the one you used when entering the building. If you require assistance in evacuation, inform your instructor in writing during the first week of class. For evacuation in your classroom or building:

Follow the instructions of faculty and teaching staff.
Exit in an orderly fashion and assemble outside.
Do not re-enter a building unless given instructions by emergency personnel.

Emergency evacuation route information and emergency procedures can be found at:

 http://www.utexas.edu/emergency     &     http://www.utexas.edu/safety/preparedness/


Copyright 2001 - 2017 Mark McDermott


Last updated:  Tuesday, April 04, 2017 10:49 AM