Spring 2018

EE 382N-4: Advanced Micro-Controller Systems

Classroom: ECJ 1.308 

Time: T/Th  14:00 - 15:30


Course Goals:

This course focuses on the HW/SW architectures of “System-on-a-Chip (SoC) implementations. These SoC’s are composed of hardware and software components which must be seamlessly integrated together to produce working SOCs. These systems are becoming increasingly complex utilizing micro-architectural features from high performance computing platforms and from operating systems such as Linux and Android.

Topics covered include:

Hardware and software co-design of an SOC on a Dual-ARM core based FPGA

Linux drivers/handlers, kernel modules and interrupt handlers

RTOS, Middleware, SW Library development,

Flash based file systems

Embedded Linux debugging

Hardware accelerators, dataflow processing & fuzzy logic acceleration

Intelligent & cognitive sensor systems, sensor fusing

I/O subsystems

Networking-on-chip (NOC).

There will be 3 lab assignments, 2 exams and a class project.

The class project focuses building a hardware accelerator that is coupled to a dual ARM core system via the AXI bus using the ZYNQ-7020 programmable SOC on the ZEDBOARD.

The Lab assignments focus on learning how to design, synthesize, debug and test various components of the ZYNQ SOC.

 

 

 

 

 


Course prerequisites: 

EE 360N undergraduate Computer Architecture, or an equivalent undergraduate computer architecture class.

EE445L or EE445M undergraduate Embedded Systems Labs, or similar courses.

Basic assembly language programming skills (ARM)

Basic VERILOG programming skills

Basic high level language programming skills such as C or C++

Some familiarity with Linux programming


Instructors:

Mark McDermott
Office: EER 5.826, Phone: (512) 471-3253
Office hours: TBD

E-Mail:


TA:

TBD


Course outline and schedule:

Week Date Lecture Topic Lecture Notes LAB Assignments

1

Jan 16

Introduction

Lecture 1

LAB #1

Due Feb 8th

Jan 18

Xilinx Programming Environment

Lecture 2

2

Jan 23

Xilinx Zynq-7000 Architecture

Lecture 3

Jan 25

3

Jan 30

ARM Processor Micro-Architecture

Lecture 4

Feb 1

ARM Instruction Set Architecture

Lecture 5

4

Feb 6

ARM SW Programming

Lecture 6

Feb 8

Hardware Accelerators

Lecture 7

LAB #2

Due Mar 8th

5

Feb 13

Embedded Linux

Lecture 8

Feb 15

6

Feb 20

Linux Device Drivers

Lecture 9

Feb 22

7

Feb 27

Interrupts & Interrupt Handlers

Lecture 10

Mar 1

Debugging Embedded Linux

Lecture 11

8

Mar 6

Boot Loaders & Device Tree Blobs

Lecture 12

LAB #3

Due Apr 5th

 

Mar 8

Exam #1

 

Spring Break

10

Mar 20

Dataflow Processing

Lecture 13

Mar 22

11

Mar 27

Intelligent & Cognitive Sensor Systems

Lecture 14

Mar 29

12

Apr 3

Embedded File Systems

Lecture 15

Apr 5

Real Time Operating Systems

Lecture 16

 

13

Apr 10

I/O Subsystems

Lecture 17

Apr 12

DSP Architectures

Lecture 18

14

Apr 17

Embedded Software Optimization

Lecture 19

Apr 19

 FPGA Architectures

Lecture 20

15

Apr 24

Networks-on-Chips 

Lecture 21

Apr 26

Exam #2

 

16

May 1

FINAL PROJECT DESIGN REVIEWS

May 3

  Grading:

Labs 30%
Exam #1 15%
Exam #2 15%
Project 40%

 

Late Submission Penalties:

Penalty for late submission of Labs and Class Project: 25% per working day (Maximum: 100%)

 

Lab Facilities:

EER 1.810

 


Digilent Zedboard Documentation

Creating a Custom IP core using the IP Integrator

Getting Started with Zynq

Using Pmod IPs

Zedboard DMA Audio Demo

Zedboard LED Demo

Zedboard OLED Demo

Zedboard Programming Guide in SDK

Xilinx Zynq-7000 and Vivado Documentation

ZYNQ Video Tutorials

Vivado Video Tutorials

Vivado Design Suite Tutorial (UG940)

Vivado Design Suite Tutorial: Programming and Debugging

Vivado Design Suite Tutorial: High-Level Synthesis

Introduction to FPGA Design with Vivado High-Level Synthesis

Vivado Design Suite User Guide: High-Level Synthesis

Zynq-7000 All Programmable SoC Technical Reference Manual

AXI Infrastructure Intellectual Property

Vivado Design Suite User Guide: Synthesis (UG901)

Vivado Design Suite User Guide: Implementation (UG904)

Vivado Design User Guide: Design Flows Overview (UG892)

Debugging U-Boot with SDK

Creating and AXI Peripheral

Using Xilinx SDK

 

Xilinx Wiki

Main page

Linux

U-Boot

Technical Articles

Installing Ubuntu

Zynq Base Targeted Reference Design (TRD)

Forums

Xilinx

Avnet

Digilent

 

Useful Websites

An FPGA Tutorial using the ZedBoard

Zynq Design from Scratch

Zynq Development

Free Electrons

Zynq Training

 


Reference Books:

Sreekrishnan Venkateswaran   Essential Linux Device Drivers (Prentice Hall Open Source Software Development Series)

Karim Yaghmour    Building Embedded Linux Systems

Jonathon Corbet    Linux Device Drivers

Richard Zurawski    Embedded Systems Handbook: Networked Embedded Systems

Richard Zurawski   Embedded Systems Handbook: Embedded Systems Design and Verification

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book: Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, PDF copy available for free at http://www.zynqbook.com

L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W. Stewart, The Zynq Book Tutorials, available for free at http://www.zynqbook.com/download-tuts.html

 


 

Academic dishonesty:


Oral discussion of homework problems is encouraged. However, be sure to submit your own individual and independent solution. Labs and final projects can be done in teams. Collaboration on projects is encouraged. Copying of any part of a homework/lab solution or project report without explicit reference to its source is plagiarism and considered cheating.

Electronic Mail Notification Policy:

In this course e-mail will be used as a means of communication with students. You will be responsible for checking your e-mail regularly for class work and announcements. The complete text of the University electronic mail notification policy and instructions for updating your e-mail address are available at http://www.utexas.edu/its/policies/emailnotify.html


Use of Canvas and Class Web Site

This course uses the class web page and Canvas to distribute course materials, to communicate and collaborate online, to submit assignments and to post solutions and grades. You will be responsible for checking the class web page and the Canvas course site regularly for class work and announcements. As with all computer systems, there are occasional scheduled downtimes as well as unanticipated disruptions. Notification of disruptions will be posted on the Canvas login page. Scheduled downtimes are not an excuse for late work. However, if there is an unscheduled downtime for a significant period of time, I will make an adjustment if it occurs close to the due date.


Students with disabilities

The University of Texas at Austin provides upon request appropriate academic accommodations for qualified students with disabilities. For more information, contact the Services for Students with Disabilities (SSD) at 471-6259, http://ddce.utexas.edu/disability/.


Religious Holidays

Religious holy days sometimes conflict with class and examination schedules. If you miss an examination, work assignment, or other project due to the observance of a religious holy day you will be given an opportunity to complete the work missed within a reasonable time after the absence. It is the policy of The University of Texas at Austin that you must notify each of your instructors at least fourteen days prior to the classes scheduled on dates you will be absent to observe a religious holy day.


Classroom Evacuation and Emergency Preparedness

All occupants of university buildings are required to evacuate a building when a fire alarm and/ or an official announcement is made indicating a potentially dangerous situation within the building. Familiarize yourself with all exit doors of each classroom and building you may occupy. Remember that the nearest exit door may not be the one you used when entering the building. If you require assistance in evacuation, inform your instructor in writing during the first week of class. For evacuation in your classroom or building:

Follow the instructions of faculty and teaching staff.
Exit in an orderly fashion and assemble outside.
Do not re-enter a building unless given instructions by emergency personnel.

Emergency evacuation route information and emergency procedures can be found at:

 http://www.utexas.edu/emergency     &     http://www.utexas.edu/safety/preparedness/


Copyright 2001 - 2017 Mark McDermott

 


Last updated:  Thursday, November 16, 2017 07:54 AM