Mattan Erez - Publications

• Refereed Papers
  
• Invited Talks
  
• Issued Patents
  
• Technical Reports
  
• In Preparation
  

• Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez, Li-Shiuan Peh, "NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication", in the Sixteenth IEEE Symposium on High-Performance Interconnects (HotI-16), Stanford, CA, August, 2008.
   
• Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally, "Architectural Support for the Stream Execution Model on General-Purpose Processors", in the Proceedings of the 16th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'07), Brasov, Romania, September 15-19, 2007.
   
• Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, and William J. Dally, "Executing Irregular Scientific Applications on Stream Architectures", in the proceedings of the 21st ACM International Conference on Supercomputing (ICS'07), Seattle, Washington, June 2007.
   
• Jung Ho Ahn, William J. Dally, and Mattan Erez, "Tradeoff between Data-, Instruction-, and Thread-level Parallelism in Stream Processors", in the proceedings of the 21st ACM International Conference on Supercomputing (ICS'07), Seattle, Washington, June 2007.
   
• Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, and Pat Hanrahan, "Compilation for Explicitly Managed Memory Hierarchies", in the proceedings of the 2007 Symposium on Principles and Practice of Parallel Programming (PPoPP'07), San Jose, California, March 2007.
   
• Kayvon Fatahalian, Timothy J. Knight, Mike Houston, Mattan Erez, Daniel Reiter Horn, Larkhoon Leem, Ji Young Park, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan, "Programming the Memory Hierarchy", in the proceedings of the 2006 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'06), Tampa, Florida, November 2006.
   
• Jung Ho Ahn, Mattan Erez, William J. Dally, "The Design Space of Data-Parallel Memory Systems", in the proceedings of the 2006 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'06), Tampa, Florida, November 2006.
   
• Ulrich Barnhoefer, Moon-Jung Kim, Mattan Erez, "A Low Power, Passively Cooled 2000cd/m2 Hybrid LED-LCD Display", in the proceedings of the IEEE International Symposium on Consumer Electronics 2006, St. Petersburg, Russia, June 2006.
  best paper award
   
• Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally, "Fault Tolerance Techniques for the Merrimac Streaming Supercomputer", in the proceeding of the 2005 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'05), Seattle, Washington, November 2005.
  best student paper finalist, 1 out of 4 chosen from over 40 eligible papers
   
• Jung Ho Ahn, Mattan Erez, William J. Dally, "Scatter-Add in Data Parallel Architectures", in the proceedings of the Eleventh International Symposium on High-Performance Computer Architecture (HPCA-11), San Francisco, California, February 2005.
   
• Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve, "Analysis and Performance Results of a Molecular Modeling Application on Merrimac", in the proceeding of the 2004 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'04), Pittsburgh, Pennsylvania, November 2004.
  best student paper award, chosen from over 40 eligible papers
   
• Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally, "Stream Register Files with Indexed Access", in the proceedings of the Tenth International Symposium on High-Performance Computer Architecture (HPCA-10), Madrid, Spain, February 2004.
   
• William J. Dally, Patrick Hanrahan, Mattan Erez, Timothy J. Knight, François Labonté, Jung Ho Ahn, Nuwan Jayasena, Ujval J. Kapasi, Abhishek Das, Jayanth Gummaraju, Ian Buck, "Merrimac: Supercomputing with Streams", in the proceeding of the 2003 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC'03), Phoenix, Arizona, November 2003.
  best paper finalist, 1 out of 5 chosen from over 60 eligible papers
   
• Stephan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen, "eXtended Block Cache", in the proceedings of the Sixth International Symposium on High-Performance Computer Architecture (HPCA-6), Toulouse, France, January 2000.
   
• Adi Yoaz, Mattan Erez, Ronny Ronen, Stephan Jourdan, "Speculation Techniques for Improving Load Related Instruction Scheduling", in the proceedings of the 26th International Symposium on Computer Architecture (ISCA-26), Atlanta, Georgia, May 1999.
   
• Adi Yoaz, Mattan Erez, Ronny Ronen, "Improved Instruction Scheduling Techniques", Intel Design & Test Technology Conference (internal), Portland Oregon, July 1998.
   

• "Stream Processing: a New HW/SW Contract for High-Performance Efficient Computation" CScADS Workshop on Automatic Tuning, Snowbird, UT, July 11, 2007.
   
• "Stream Architectures - Programmability and Efficiency", International Symposium on System-on-Chip 2004, Tampere, Finland, November 17, 2004.
   

• Adi Yoaz, Ronny Ronen, Lihu Rappoport, Mattan Erez, Stephan Jourdan, Robert Valentine, "Memory Cache Bank Prediction", US Patent #6,880,063, Issued April 12, 2005 (Intel Corporation).
   
• Adi Yoaz, Gregory Pribush, Freddy Gabbay, Mattan Erez, Ronny Ronen, "Fast Branch Misprediction Recovery Method and System", US Patent #6,757,816, Issued June 29, 2004 (Intel Corporation).
   
• Adi Yoaz, Mattan Erez, Ronny Ronen, "System and Method for Early Resolution of Low Confidence Branches and Safe Data Cache Accesses", US Patent #6,697,932, Issued February 24, 2004 (Intel Corporation).
   
• Adi Yoaz, Ronny Ronen, Lihu Rappoport, Mattan Erez, Stephan Jourdan, Robert Valentine, " Cache Memory Bank Access Prediction", US Patent #6,694,421, Issued February 17, 2004 (Intel Corporation).
   

• Mattan Erez, "Merrimac -- High-Performance, Highly-Efficient Scientific Computing with Streams", Ph.D. dissertation, November 2006, Stanford University, Stanford, California.
   
• Mattan Erez, Brian Towles, William J. Dally, " Spills, Fills, and Kills - An Architecture for Reducing Register-Memory Traffic", Concurrent VLSI Architecture Technical Report (TR23), Stanford, California, November 2000 (ftp://cva.stanford.edu/pub/publications/sfka_TR23.pdf).