J. Miao, A.
Gerstlauer, and M. Orshansky, "Multi-level
approximate logic synthesis under general error constraints,"
Proc. of International Conference on Computer-Aided Design (ICCAD), Nov.
2014.
K. He, A.
Gerstlauer, and M. Orshansky, “Circuit-Level
Timing-Error Acceptance for Design of Energy Efficient DCT/IDCT-Based
Systems,” IEEE
Transactions on Circuits and Systems for Video Technology, vol. 23, no. 6,
pp. 961-974, Jan. 2013.
J. Miao, A.
Gerstlauer, and M. Orshansky, “Approximate Logic Synthesis under General
Error Magnitude and Frequency Constraints,” Proc. of International
Conference on Computer-Aided Design (ICCAD), Nov. 2013.
J. Han and M.
Orshansky, “Approximate Computing: an Emerging Paradigm for Energy-Efficient
Design,” Proc. of European Test Symposium, May 2013, invited.
K. He, A. Gerstlauer, and M. Orshansky, “Low-Energy Digital Filter Design Based on Controlled Timing Error Acceptance,” Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2013.
J. Miao, K.
He, A. Gerstlauer, and M. Orshansky, “Modeling and
Synthesis of Quality-Energy Optimal Approximate Adders,”
Proc. of International Conference on Computer-Aided Design (ICCAD), pp.
728-735, San Jose, CA, Nov. 2012.
K. He, A.
Gerstlauer, and M. Orshansky, “Low-Energy Signal
Processing using Circuit-Level Timing-Error Acceptance,”
Proc. of IEEE International Conference on IC Design and Technology, pp. 1-4,
Austin, TX, May-June 2012, invited.
K. He, A. Gerstlauer, and M. Orshansky, “Controlled Timing-Error Acceptance for Low Energy IDCT Design,” Proc. of Design Automation and Test in Europe, pp. 1-6, Grenoble, France, March 2011.
N. R.
Shanbhag, S. Mitra, G. de Veciana, M. Orshansky, R. Marculescu, J.
Roychowdhury, D. Jones, and J. M. Rabaey, “The
Search for Alternative Computational Paradigms,”
IEEE Design and Test, vol. 25, no. 4, pp. 334-343, Jul.-Aug. 2008.