S. Banerjee,
K. B. Agarwal, S. Nassif, and M. Orshansky, “Methods for Joint
Optimization of Mask and Design Targets for Improving Lithographic Process
Window,” SPIE
Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12, no. 2,
June 2013.
S. Banerjee,
K. B. Agarwal, S. Nassif, and M. Orshansky, “Shape Slack: A
Design-Manufacturing Co-optimization Methodology using Tolerance Information,”
SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12, no.
1, Feb. 2013.
S. Banerjee,
K. B. Agarwal, and M. Orshansky, “Simultaneous
OPC and Decomposition for Double Exposure Lithography,”
Proceedings of SPIE, pp. 79730E, San Jose, CA, Feb. 2011.
S. Banerjee,
K. B. Agarwal, S. Nassif, J. A. Culp, L. W. Liebmann, and M. Orshansky, “Coupling Timing
Objectives with Optical Proximity Correction for Improved Timing Yield,”
Proc. of International Symposium on Quality of Electronic Design, pp. 1-6,
Santa Clara, CA, March 2011.
S. Banerjee, K. B. Agarwal, and M. Orshansky, “SMATO: Simultaneous Mask and Target Optimization for Improving Lithographic Process Window,” Proc. of International Conference on Computer-Aided Design, pp. 100-106, San Jose, CA, Nov. 2010.
S. Banerjee,
K. Agarwal, and M. Orshansky, “Ground Rule Slack
Aware Tolerance-Driven Optical Proximity Correction for Local Metal
Interconnects,”
Proc. of Custom Integrated Circuits Conference, pp. 1-4, San Jose, CA, Sept.
2010.
S. Banerjee,
K. B. Agarwal, C.-N. Sze, S. Nassif and M. Orshansky, “A Methodology for
Propagating Design Tolerances to Shape Tolerances for Use in Manufacturing,”
Design Automation and Test in Europe, pp. 1273-1278, Dresden, Germany, March
2010. Best Paper Award Nomination.
S. Banerjee, K. B. Agarwal, J. A. Culp, P. Elakkumanan, L. W. Liebmann, and M. Orshansky, “Compensating Non-Optical Effects Using Electrically Driven Optical Proximity Correction,” Proc. of SPIE, pp. 7275, San Jose, CA, Feb. 2009.
S. Banerjee,
P. Elakkumanan, L. W. Liebmann, and M. Orshansky, “Electrically Driven
Optical Proximity Correction Based on Linear Programming,”
Proc. of IEEE/ACM International Conference on Computer Aided Design, pp.
473-479, San Jose, CA, Nov. 2008.
S. Banerjee,
P. Elakkumanan, D. Chidambarrao, J. Culp, and M. Orshansky, “Analysis
of Systematic Variation and Impact on Circuit Performance,”
SPIE Symposium on Advanced Lithography, pp. 69250K, San Jose, CA, Feb. 2008.
S. Banerjee, P. Elakkumanan, L. W. Liebmann, J. Culp, and M. Orshansky, “Electrically Driven Optical Proximity Correction,” SPIE Symposium on Advanced Lithography, pp. 69251W, San Jose, CA, Feb. 2008.
M. Orshansky, L. Milor, and C. Hu, “Characterization of Spatial Intrafield Gate CD Variability, Its Impact
on Circuit Performance, and Spatial Mask-Level Correction,” IEEE
Transactions on Semiconductor Manufacturing, vol. 17, no. 1, pp. 2-11, Feb.
2004, Best Paper Award.
M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu,
“Impact of Systematic Spatial Intra-Chip Gate Length Variability on
Performance of High-Speed Digital Circuits,” Proc. of IEEE/ACM
International Conference on Computer Aided Design, pp. 62-27, San Jose, CA,
Nov. 2000.
M. Orshansky, L. Milor, M. Brodsky, L. Nguyen, G. Hill,
Y.-K. Peng, and C. Hu, “Characterization
of Spatial CD Variability, Spatial Mask-Level Correction, and Improvement of
Circuit Performance,” Proc. of SPIE Conference on Optical
Microlithography, Vol. 4000, pp. 602-611, Santa Clara, CA, July 2000.
M. Orshansky, L. Milor, L. Nguyen, G. Hill, Y. Peng, and C. Hu, “Intra-Field Gate CD Variability and Its Impact on Circuit Performance,” Proc. of IEEE International Electron Devices Meeting, pp. 479-82, Washington D.C., Dec. 1999.