2018

X. Xi, A. Aysu and M. Orshansky, “Fresh Re-keying with Strong PUFs: A New Approach to Side-Channel Security,” to appear at HOST, 2018.
A. Aysu, M. Tiwari, and M. Orshansky, “Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols,” to appear at HOST, 2018.
A. Aysu, M. Orshansky, and M. Tiwari, “A Novel Hardware Design for Binary Ring-LWE with Power Side-channel Resilience,” to appear at Design Automation and Test in Europe (DATE), 2018.
Y. Wang and M. Orshansky, “Efficient Helper Data Reduction in SRAM PUFs via Lossy Compression,” to appear at Design Automation and Test in Europe (DATE), 2018.

2017

A. Kumar, C. Scarborough, A. Yilmaz and M. Orshansky, “Efficient Simulation of EM Side-Channel Attack Resilience,” International Conference on Computer-Aided Design (ICCAD), Nov. 2017. Best Paper Award Nomination.
X. Xi, H. Zhang, N. Sun, and M. Orshansky, “Strong Subthreshold Current Array PUF with 2⁶⁵ Challenge-Response Pairs Resilient to Machine Learning Attacks in 130nm CMOS,” Proc. of VLSI Circuits Symposium, Kyoto, Japan, June 2017.
S. Jeloka, K. Yang, M. Orshansky, D. Sylvester, D. Blaauw, “A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell,” In VLSI Circuits Symposium, 2017.
A. Aysu, W. Wang, P. Schaumont, and M. Orshansky, “A new maskless debiasing method for lightweight physical unclonable functions,” Proc. of Hardware-Oriented Security and Trust (HOST), May 2017.

2016

Y. Wang, C. Caramanis, and M. Orshansky, “Exploiting randomness in sketching for efficient hardware implementation of machine learning applications,” Proc. of ICCAD, Nov. 2016.
M. Li, Y. Wang, and M. Orshansky, “A Monte Carlo Simulation Flow for SEU Analysis of Sequential Circuits,” Proc. of Design Automation Conference, June 2016.
Y. Wang, M. Orshansky, and C. Caramanis, “PolyGP: Improving GP-Based Analog Optimization through Accurate High-Order Monomials and Semidefinite Relaxation,” Design Automation and Test in Europe Conference (DATE), March 2016.
J. Park and M. Orshansky, “Multiple Attempt Write Strategy for Low Energy STT-RAM,” Great Lakes Symposium on VLSI, May 2016.

2015

Y. Wang, M. Orshansky, and C. Caramanis, “PolyGP: Improving GP-Based Analog Optimization through Accurate High-Order Monomials and Semidefinite Relaxation,” Frontiers in Analog CAD (FAC) International Workshop on Design Automation for Analog and Mixed-Signal Circuits, Nov. 2015.
Y. Wang, M. Li, X. Yi, Z. Song, M. Orshansky, and C. Caramanis, “Novel Power Grid Reduction Method based on L1 Regularization,” Proc. of Design Automation Conference, 2015.
J. Park, T. Zheng, M. Erez, and M. Orshansky, “Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture,” IEEE Transactions on VLSI, no. 7, pp. 1, 2015.

2014

J. Miao, A. Gerstlauer, and M. Orshansky, “Multi-Level Approximate Logic Synthesis under General Error Constraints,” Proc. of International Conference on Computer-Aided Design (ICCAD), Nov. 2014.
Y. Wang, M. Orshansky, and C. Caramanis, “Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization,” Proc. of Design Automation Conference, 2014.
A. K. Singh, K. He, C. Caramanis, and M. Orshansky, “Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, no.8, pp. 1159-1167, 2014.

2013

S. Banerjee, K. B. Agarwal, S. Nassif, and M. Orshansky, “Methods for Joint Optimization of Mask and Design Targets for Improving Lithographic Process Window,” SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12, no. 2, June 2013.
S. Banerjee, K. B. Agarwal, S. Nassif, and M. Orshansky, “Shape Slack: A Design-Manufacturing Co-optimization Methodology using Tolerance Information,” SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 12, no. 1, Feb. 2013.
K. He, A. Gerstlauer, and M. Orshansky, “Circuit-Level Timing-Error Acceptance for Design of Energy Efficient DCT/IDCT-Based Systems,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 23, no. 6, pp. 961-974, Jan. 2013.
M. Yousofshahi, M. Orshansky, K. Lee, and S. Hassoun, “Probabilistic Strain Optimization under Constraint Uncertainty,” BMC Systems Biology, vol. 7, no. 29, pp. 1-13, 2013. Highly accessed.
J. Miao, A. Gerstlauer, and M. Orshansky, “Approximate Logic Synthesis under General Error Magnitude and Frequency Constraints,” Proc. of International Conference on Computer-Aided Design (ICCAD), Nov. 2013.
T. Zheng, J. Park, M. Orshansky, and M. Erez, “Variable-Energy Write STT-RAM Architecture with Bit-Wise Write-Completion Monitoring,” Proc. of IEEE International Symposium on Low-Power Design, Aug. 2013.
J. Han and M. Orshansky, “Approximate Computing: an Emerging Paradigm for Energy-Efficient Design,” Proc. of European Test Symposium, May 2013, invited.
M. Kalyanaraman and M. Orshansky, “Novel Strong PUF Based on Nonlinearity of MOSFET Subthreshold Operation,” Proc. of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), June 2013. Best Paper Award Nomination.
M. Yousofshahi, M. Orshansky, K. Lee, and S. Hassoun, “Gene Modification Identification under Flux Capacity Uncertainty,” Proc. of Design Automation Conference, No. 45, Austin, TX, June 2013.
K. He, A. Gerstlauer, and M. Orshansky, “Low-Energy Digital Filter Design Based on Controlled Timing Error Acceptance,” Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2013.

2012

A. K. Singh, K. Ragab, M. Lok, C. Caramanis, and M. Orshansky, “Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics,” IEEE Transactions on Computer Aided Design of Integrated Circuits, vol. 31, no. 10, pp. 1485-1498, Oct. 2012.
J. Miao, K. He, A. Gerstlauer, and M. Orshansky, “Modeling and Synthesis of Quality-Energy Optimal Approximate Adders,” Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 728-735, San Jose, CA, Nov. 2012.
K. He, A. Gerstlauer, and M. Orshansky, “Low-Energy Signal Processing using Circuit-Level Timing-Error Acceptance,” Proc. of IEEE International Conference on IC Design and Technology, pp. 1-4, Austin, TX, May-June 2012, invited.
K. Ragab, R. Gharpurey, and M. Orshansky, “Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: Design Methodology and Implementation,” Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 143-150, Santa Clara, CA, March 2012.
J. Park and M. Orshansky, “Abnormal ESD Failure Mode with Low-Voltage Turn-on Phenomenon of LDMOS Output Driver,” Proc. of International Reliability Physics Symposium, EL.1.1-EL.1.4, Anaheim, CA, April 2012.

2011

A. Ramalingam, G. J. Nam, A. K. Singh, M. Orshansky, S. R. Nassif, and D. Z. Pan, “An Accurate Sparse M Based Framework for Statistical Static Timing Analysis,” Integration, the VLSI Journal, pp. 231-236, March 2011.
K. He, A. Gerstlauer, and M. Orshansky, “Controlled Timing-Error Acceptance for Low Energy IDCT Design,” Proc. of Design Automation and Test in Europe, pp. 1-6, Grenoble, France, March 2011.
S. Banerjee, K. B. Agarwal, and M. Orshansky, “Simultaneous OPC and Decomposition for Double Exposure Lithography,” Proceedings of SPIE, pp. 79730E, San Jose, CA, Feb. 2011.
S. Banerjee, K. B. Agarwal, S. Nassif, J. A. Culp, L. W. Liebmann, and M. Orshansky, “Coupling Timing Objectives with Optical Proximity Correction for Improved Timing Yield,” Proc. of International Symposium on Quality of Electronic Design, pp. 1-6, Santa Clara, CA, March 2011.

2010

A. K. Singh, M. Lok, C. Caramanis, and M. Orshansky, “An Algorithm for Exploiting Modeling Error Statistics to Enable Robust Analog Optimization,” Proc. of International Conference on Computer-Aided Design, pp. 62-69, San Jose, CA, Nov. 2010.
S. Banerjee, K. B. Agarwal, and M. Orshansky, “SMATO: Simultaneous Mask and Target Optimization for Improving Lithographic Process Window,” Proc. of International Conference on Computer-Aided Design, pp. 100-106, San Jose, CA, Nov. 2010.
M. Lok, K. He, M. Mani, C. Caramanis, and M. Orshansky, “Design of Power-Optimal Buffers Tunable to Process Variability,” IEEE Dallas Circuits and Systems Workshop, pp. 1-4, Richardson, TX, Oct. 2010.
S. Banerjee, K. Agarwal, and M. Orshansky, “Ground Rule Slack Aware Tolerance-Driven Optical Proximity Correction for Local Metal Interconnects,” Proc. of Custom Integrated Circuits Conference, pp. 1-4, San Jose, CA, Sept. 2010.
M. Basoglu, M. Orshansky, and M. Erez, “NBTI-Aware DVFS: A New Approach to Saving Energy and Increasing Processor Lifetime,” Proc. of IEEE International Symposium on Low-Power Design, pp. 253-258, Austin, TX, Aug. 2010.
S. Banerjee, K. B. Agarwal, C.-N. Sze, S. Nassif and M. Orshansky, “A Methodology for Propagating Design Tolerances to Shape Tolerances for Use in Manufacturing,” Design Automation and Test in Europe, pp. 1273-1278, Dresden, Germany, March 2010. Best Paper Award Nomination.

2009

M. Orshansky and W.-S. Wang, “Statistical Analysis of Circuit Timing Using Majorization,” Communications of the ACM (CACM), vol. 52, no. 8, pp. 95-100, Aug. 2009.
A. K. Singh, K. He, C. Caramanis, and M. Orshansky, “Mitigation of Intra-Array SRAM Variability using Adaptive Voltage Architecture,” Proc. of IEEE/ACM International Conference on Computer- Aided Design, pp. 637-644, San Jose, CA, Nov. 2009.
S. Banerjee, K. B. Agarwal, J. A. Culp, P. Elakkumanan, L. W. Liebmann, and M. Orshansky, “Compensating Non-Optical Effects Using Electrically Driven Optical Proximity Correction,” Proc. of SPIE, pp. 7275, San Jose, CA, Feb. 2009.

2008

N. R. Shanbhag, S. Mitra, G. de Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, and J. M. Rabaey, “The Search for Alternative Computational Paradigms,” IEEE Design and Test, vol. 25, no. 4, pp. 334-343, Jul.-Aug. 2008.
S. Banerjee, P. Elakkumanan, L. W. Liebmann, and M. Orshansky, “Electrically Driven Optical Proximity Correction Based on Linear Programming,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 473-479, San Jose, CA, Nov. 2008.
A. K. Singh and M. Orshansky, “Logic Synthesis for Reducing Leakage Power Consumption under Workload Uncertainty,” International Conference on Circuits, pp. 351-355, Heraklion, Greece, July 2008.
B. Zhang and M. Orshansky, “Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 774-779. San Jose, CA, March 2008.
S. Banerjee, P. Elakkumanan, D. Chidambarrao, J. Culp, and M. Orshansky, “Analysis of Systematic Variation and Impact on Circuit Performance,” SPIE Symposium on Advanced Lithography, pp. 69250K, San Jose, CA, Feb. 2008.
S. Banerjee, P. Elakkumanan, L. W. Liebmann, J. Culp, and M. Orshansky, “Electrically Driven Optical Proximity Correction,” SPIE Symposium on Advanced Lithography, pp. 69251W, San Jose, CA, Feb. 2008.

2007

M. Mani, A. Devgan, M. Orshansky, and Y. Zhan, “A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 26, no. 10, pp. 1790-1802, Oct. 2007.
W.-S. Wang and M. Orshansky, “Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters,” ASP Journal of Low Power Electronics, vol. 3, no. 1, pp. 1-12, April 2007.
K. Constantinides, S. Plaza, J. Blome, V. Bertacco, S. Mahlke, T. Austin, B. Zhang, and M. Orshansky, “Architecting a Reliable CMP Switch Architecture,” ACM Transactions on Architecture and Code Optimization, vol. 4, no. 1, pp. 1-37, March 2007.
A. Singh, H. A. Hady Zeineddine, A. Aziz, S. Vishwanath, and M. Orshansky, “A Heterogeneous CMOS-CNT Architecture utilizing Novel Coding of Boolean Functions,” Proc. of IEEE/ACM Symposium on Nanoscale Architectures, pp. 15-20, San Jose, CA, Oct. 2007.
A. Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and D. Z. Pan, “Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis,” Proc. of ACM/IEEE Design Automation Conference, pp. 148-153, San Diego, CA, June 2007.
R. G. Tayade, V. K. Kalyanam, S. Nassif, M. Orshansky, and J. Abraham, “Estimating Path Delay Distribution Considering Coupling Noise,” Proc. of ACM Great Lake Symposium on VLSI, pp. 61-66, Stresa-Lago Maggiore, Italy, April 2007.

2006

W.-S Wang and M. Orshansky, “Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2976-2988, Dec. 2006.
W.-S. Wang, M. Liu, and M. Orshansky, “Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation,” ASP Journal of Low Power Electronics, vol. 2, no. 1, pp. 1–7, April 2006.
M. Mani, A. Singh, and M. Orshansky, “Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 19-26, San Jose, CA, Nov. 2006. Best Paper Award.
B. Zhang, A. Arapostathis, S. Nassif, and M. Orshansky, “Analytical Modeling of SRAM Dynamic Stability,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 315-322, San Jose, CA, Nov. 2006.
A. Ramalingam, G.-J. Nam, A. K. Singh, M. Orshansky, S. R. Nassif, and D. Z. Pan, “An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 231-236, San Jose, CA, Nov. 2006.
W.-S. Wang and M. Orshansky, “Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 884-890, San Jose, CA, Nov. 2006.
W.-S. Wang, V. Kreinovich, and M. Orshansky, “Statistical Timing Based on Incomplete Probabilistic Descriptions of Parameter Uncertainty,” Proc. of ACM/IEEE Design Automation Conference, pp. 161-166, San Francisco, CA, July 2006.
A. K. Singh, M. Mani, R. Puri, and M. Orshansky, “Gain-Based Technology Mapping for Minimum Runtime Leakage under Input Vector Uncertainty,” Proc. of ACM/IEEE Design Automation Conference, pp. 522-527, San Francisco, CA, July 2006.
M. Orshansky, “Statistical Minimization of Total Power under Timing Yield Constraints,” in Proc. of IEEE International Conference on IC Design and Technology, pp. 1-4, Padova, Italy, May 2006, Invited.
M. Orshansky, W.-S. Wang, M. Ceberio, and G. Xiang, “Interval-Based Robust Statistical Techniques for Non-Negative Convex Functions, with Application to Timing Analysis of Computer Chips,” Proc. of ACM Symposium on Applied Computing, pp. 1645-1649, Dijon, France, April 2006.
J. Kim and M. Orshansky, “Towards Formal Probabilistic Power-Performance Design Space Exploration,” Proc. of ACM Great Lake Symposium on VLSI, pp. 229-234, Philadelphia, PA, April 2006.
M. Mani, M. Sharma, and M. Orshansky, “Application of Fast SOCP-based Statistical Sizing in the Microprocessor Design Flow,” Proc. of ACM Great Lake Symposium on VLSI, pp. 372-375, Philadelphia, PA, April 2006.
B. Zhang, W.-S. Wang, and M. Orshansky, “FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs,” Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 755-760, San Jose, CA, March 2006. Best Paper Award.
K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, “BulletProof: A DefectTolerant CMP Switch Architecture,” Proc. of IEEE International Symposium on High Performance Computing and Applications, pp. 5-16, Austin, Texas, Feb. 2006.

2005

A. K. Singh, M. Mani, and M. Orshansky, “Statistical Technology Mapping for Parametric Yield,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 511-518, San Jose, CA, Nov. 2005.
M. Mani, A. Devgan, and M. Orshansky, “An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints,” Proc. of ACM/IEEE Design Automation Conference, pp. 309-314, Anaheim, CA, June 2005. Best Paper Award.

2004

M. Orshansky, L. Milor, and C. Hu, “Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction,” IEEE Transactions on Semiconductor Manufacturing, vol. 17, no. 1, pp. 2-11, Feb. 2004, Best Paper Award.
M. Mani and M. Orshansky, “A New Statistical Optimization Algorithm for Gate Sizing,” Proc. of IEEE International Conference on Computer Design, pp. 272-277, San Jose, CA, Oct. 2004.
M. Liu, W.-S. Wang, and M. Orshansky, “Leakage Power Reduction by Dual-Vth Designs under Probabilistic Analysis of Vth Variation,” Proc. of IEEE International Symposium on Low-Power Design, pp. 2-7, Monterey, CA, Aug. 2004.
M. Orshansky and A. Bandyopadhyay, “Fast Statistical Timing Analysis Handling Arbitrary Delay Correlations,” Proc. of ACM/IEEE Design Automation Conference, pp. 337-332, San Diego, CA, June 2004.
M. Orshansky, “Fast computation of circuit delay probability distribution for timing graphs with arbitrary node correlation Proc. of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 9-16, Austin, TX, Feb. 2004. Digital link not available.

2003-1997

Y. Cao, M. Orshansky, D. Sylvester, T. Sato, and C. Hu, “Spice up your MOSFET Modeling,” IEEE Circuits and Devices Magazine, vol. 19, no. 4, pp. 17-23, July 2003.
D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer, “Minimization of Dynamic and Static Power through Joint Assignment of Threshold Voltages and Sizing Optimization,” Proc. of IEEE International Symposium on Low Power Design, pp. 158-163, Seoul, Korea, Aug. 2003.
M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, “Impact of Systematic Spatial Intrachip Gate Length Variability on Performance of High-Speed Digital Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 21, no. 5, pp. 544-53, May 2002.
M. Orshansky and K. Keutzer, “A General Probabilistic Framework for Worst Case Timing Analysis,” Proc. of ACM/IEEE Design Automation Conference, pp. 556-561, New Orleans, LA, June 2002.
K. Keutzer and M. Orshansky, “From Blind Certainty to Informed Uncertainty,” Proc. of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 37-41, Monterey, CA, Dec. 2002. Invited.
M. Orshansky, J. An, C. Jiang, B. Liu, C. Riccobene, and C. Hu, “Efficient Generation of Pre-Silicon MOS Model Parameters for Early Circuit Design,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp.156-59, Jan. 2001.
M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, “Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 62-27, San Jose, CA, Nov. 2000.
M. Orshansky, L. Milor, M. Brodsky, L. Nguyen, G. Hill, Y.-K. Peng, and C. Hu, “Characterization of Spatial CD Variability, Spatial Mask-Level Correction, and Improvement of Circuit Performance,” Proc. of SPIE Conference on Optical Microlithography, Vol. 4000, pp. 602-611, Santa Clara, CA, July 2000.
Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, “New Paradigm of MOSFET and Interconnect Modeling for Early Circuit Design,” Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 201-204, Orlando, FL, May 2000.
M. Orshansky, J. C. Chen, and C. Hu, “Direct Sampling Methodology for Statistical Analysis of Scaled CMOS Technologies,” IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 4, pp. 403-408, Nov. 1999.
M. Orshansky, L. Milor, L. Nguyen, G. Hill, Y. Peng, and C. Hu, “Intra-Field Gate CD Variability and Its Impact on Circuit Performance,” Proc. of IEEE International Electron Devices Meeting, pp. 479-82, Washington D.C., Dec. 1999.
M. Orshansky, C. Spanos, and C. Hu, “Circuit Performance Variability Decomposition,” Proc. of IEEE International Workshop on Statistical Metrology for VLSI Design and Fabrication, pp. 10-13, Kyoto, Japan, June 1999.
M. Orshansky, J. C. Chen, C. Hu, D. Wan, P. Bendix, “Approaches to Statistical Circuit Analysis for Deep Sub-Micron Technologies,” Proc. of IEEE International Workshop on Statistical Metrology for VLSI Design and Fabrication, pp. 6-9, Honolulu, Hawaii, June 1998.
M. Orshansky, J. C. Chen, and C. Hu, “A Statistical Performance Simulation Methodology for VLSI Circuits,” Proc. of ACM/IEEE Design Automation Conference, pp. 402-407, San Francisco, CA, June 1998.
M. Orshansky, D. Sinitsky, P. Scrobahaci, J. Bokor, and C. Hu, “Impact of Velocity Overshoot, Polysilicon Depletion, and Inversion Layer Quantization on NMOSFET Scaling,” Proc. of IEEE Device Research Conference, pp. 18-19, Charlottesville, VA, June 1998.
J. Chen, M. Orshansky, C. Hu, and C-P. Wan, “Statistical Circuit Characterization for Deep-Submicron CMOS Designs,” Proc. of IEEE International Solid-State Circuits Conference (ISSCC), pp. 90-91, San Francisco, CA, Feb. 1998.
D. Sinitsky, F. Assaderaghi, M. Orshansky, J. Bokor, and C. Hu, “Velocity Overshoot of Electrons and Holes in Si Inversion Layers,” Journal of Solid-State Electronics, vol. 41, no. 8, pp.1119-25, Aug. 1997.
W. Liu, M. Orshansky, X. Jin, K. Chen, and C. Hu, “MOSFET Intrinsic-Capacitance Related Inaccuracy in CMOS Circuit Speed Simulation,” Proc. of IEEE International Semiconductor Device Research Symposium, pp. 337-340, Charlottesville, VA, Dec. 1997. Digital link not available.
D. Sinitsky, F. Assaderaghi, M. Orshansky, J. Bokor, and C. Hu, “An Extension of BSIM3 Model Incorporating Velocity Overshoot,” Proc. of IEEE International Symposium on VLSI Technology, Systems, and Applications, pp. 307-310, Taipei, Taiwan, June 1997.