J. Park and M. Orshansky, “Abnormal ESD Failure Mode with Low-Voltage Turn-on Phenomenon of LDMOS Output Driver,” Proc. of International Reliability Physics Symposium, EL.1.1-EL.1.4, Anaheim, CA, April 2012.CA, Sept. 2010.
M. Basoglu, M. Orshansky, and M. Erez, “NBTI-Aware DVFS: A New Approach to Saving Energy and Increasing Processor Lifetime,” Proc. of IEEE International Symposium on Low-Power Design, pp. 253-258, Austin, TX, Aug. 2010.
B. Zhang and M. Orshansky, “Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 774-779. San Jose, CA, March 2008.
B. Zhang, A. Arapostathis, S. Nassif, and M. Orshansky, “Analytical Modeling of SRAM Dynamic Stability,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 315-322, San Jose, CA, Nov. 2006.
A. Ramalingam, G.-J. Nam, A. K. Singh, M. Orshansky, S. R. Nassif, and D. Z. Pan, “An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 231-236, San Jose, CA, Nov. 2006.
B. Zhang, W.-S. Wang, and M. Orshansky, “FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs,” Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 755-760, San Jose, CA, March 2006. Best Paper Award.
K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, “BulletProof: A DefectTolerant CMP Switch Architecture,” Proc. of IEEE International Symposium on High Performance Computing and Applications, pp. 5-16, Austin, Texas, Feb. 2006.