K. Ragab, R. Gharpurey, and M. Orshansky, “Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: Design Methodology and Implementation,” Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 143-150, Santa Clara, CA, March 2012.
M. Lok, K. He, M. Mani, C. Caramanis, and M. Orshansky, “Design of Power-Optimal Buffers Tunable to Process Variability,” IEEE Dallas Circuits and Systems Workshop, pp. 1-4, Richardson, TX, Oct. 2010.
A. K. Singh, K. He, C. Caramanis, and M. Orshansky, “Mitigation of Intra-Array SRAM Variability using Adaptive Voltage Architecture,” Proc. of IEEE/ACM International Conference on Computer- Aided Design, pp. 637-644, San Jose, CA, Nov. 2009.
M. Mani, A. Singh, and M. Orshansky, “Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 19-A. K. Singh, M. Mani, R. Puri, and M. Orshansky, “Gain-Based Technology Mapping for Minimum Runtime Leakage under Input Vector Uncertainty,” Proc. of ACM/IEEE Design Automation Conference, pp. 522-527, San Francisco, CA, July 2006.
A. K. Singh, M. Mani, and M. Orshansky, “Statistical Technology Mapping for Parametric Yield,” Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 511-518, San Jose, CA, Nov. 2005.
M. Mani, A. Devgan, and M. Orshansky, “An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints,” Proc. of ACM/IEEE Design Automation Conference, pp. 309-314, Anaheim, CA, June 2005. Best Paper Award.
M. Mani and M. Orshansky, “A New Statistical Optimization Algorithm for Gate Sizing,” Proc. of IEEE International Conference on Computer Design, pp. 272-277, San Jose, CA, Oct. 2004.