M. Orshansky
and W.-S. Wang, “Statistical
Analysis of Circuit Timing Using Majorization,”
Communications of the ACM (CACM), vol. 52, no. 8, pp. 95-100, Aug. 2009.
W.-S. Wang and
M. Orshansky, “Estimation
of Leakage Power Consumption and Parametric Yield Based on Realistic
Probabilistic Descriptions of Parameters,”
ASP Journal of Low Power Electronics, vol.
3, no. 1, pp. 1-12, April 2007.
A.
Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and D. Z. Pan, “Accurate Waveform Modeling using Singular Value Decomposition with
Applications to Timing Analysis,”
Proc. of ACM/IEEE Design Automation Conference, pp. 148-153, San
Diego, CA, June 2007.
R. G. Tayade, V. K. Kalyanam, S. Nassif, M. Orshansky, and J. Abraham, “Estimating Path Delay Distribution Considering Coupling Noise,” Proc. of ACM Great Lake Symposium on VLSI, pp. 61-66, Stresa-Lago Maggiore, Italy, April 2007.
W.-S Wang
and M. Orshansky, “Path-Based
Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory
and Implementation,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 25, no. 12, pp. 2976-2988, Dec. 2006.
W.-S. Wang, M. Liu, and M. Orshansky, “Analysis
of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large
Threshold Voltage Variation,” ASP Journal of Low
Power Electronics, vol. 2, no. 1, pp. 1–7, April 2006.
A. Ramalingam, G.-J. Nam, A. K. Singh, M. Orshansky, S. R. Nassif, and D. Z. Pan, “An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 231-236, San Jose, CA, Nov. 2006.
W.-S. Wang and M. Orshansky, “Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 884-890, San Jose, CA, Nov. 2006.
W.-S. Wang, V. Kreinovich, and M. Orshansky, “Statistical Timing Based on Incomplete Probabilistic Descriptions of
Parameter Uncertainty,” Proc. of ACM/IEEE Design Automation
Conference, pp. 161-166, San Francisco, CA, July 2006.
M. Orshansky, W.-S. Wang, M. Ceberio, and G. Xiang, “Interval-Based Robust Statistical Techniques for Non-Negative Convex
Functions, with Application to Timing Analysis of Computer Chips,”
Proc. of ACM Symposium on Applied Computing, pp. 1645-1649, Dijon, France,
April 2006.
J. Kim and M. Orshansky, “Towards Formal Probabilistic Power-Performance Design Space Exploration,”
Proc. of ACM Great Lake Symposium on VLSI, pp. 229-234, Philadelphia, PA,
April 2006.
M. Liu, W.-S. Wang, and M. Orshansky, “Leakage Power Reduction by Dual-Vth Designs under Probabilistic Analysis
of Vth Variation,” Proc. of IEEE International Symposium on
Low-Power Design, pp. 2-7, Monterey, CA, Aug. 2004.
M. Orshansky and A. Bandyopadhyay, “Fast Statistical Timing Analysis Handling Arbitrary Delay Correlations,”
Proc. of ACM/IEEE Design Automation Conference, pp. 337-332, San Diego, CA,
June 2004.
M. Orshansky, “Fast computation of circuit delay probability distribution for timing graphs with arbitrary node correlation Proc. of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 9-16, Austin, TX, Feb. 2004. Digital link not available.
M. Orshansky and K. Keutzer, “A General Probabilistic Framework for Worst Case Timing Analysis,”
Proc. of ACM/IEEE Design Automation Conference, pp. 556-561, New Orleans,
LA, June 2002.
K. Keutzer and M. Orshansky, “From
Blind Certainty to Informed Uncertainty,” Proc. of
ACM/IEEE International Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems, pp. 37-41, Monterey, CA, Dec. 2002. Invited.