1.
Part a.
Symbol | Address |
A | x3003 |
DONE | x3007 |
ASCII | x3008 |
B | x3009 |
Part b.
The linkage to the main program is lost when JSR B is executed.
Part c.
PC and Z Flag are part of the ISA. MDR and BEN are part of the microarchitecture.
Part d.
Part e.
We can use NOT's opcode. Note that if imm5 is x1F, XOR DR, SR1, x1F is the same as NOT DR, SR1.
2. Each tag entry requires 14 bits (1 valid bit, 1 dirty bit, 2 bits for victim/next-victim, 10 bits for tag). We need 2^12 of these entries. The total size of the tag store is ( 2^12 x 14 ) bits. The data store requires 2^19 bits.
3.
Part II.
4.
V | PFN | |
0 | ||
1 | 101 | |
0 | ||
0 | ||
0 | ||
1 | 010 | |
0 | ||
0 | ||
0 | ||
0 | ||
1 | 011 | |
0 | ||
0 | ||
1 | 001 | |
0 | ||
0 |
5.
Part b.
We need a 16-bit temporary register which gets its inputs from the system bus. We need a signal LD.T (extra control signal 1) to control when to
load this register. This register holds the data that is fetched from memory. We also need a mux in front of the A input
of the ALU. This mux should select between SR1 and the output of the temporary register. We need a control signal
for the select line of this mux (ALUMX2 - extra control signal 2).
ALUMX2 = 0 selects SR1
ALUMX2 = 1 selects T
Part c.