Department of Electrical and Computer Engineering
The University of Texas at Austin

EE 360N
Spring, 2001
Y. N. Patt, Instructor
Onur Mutlu, Kameswar Subramaniam, TAs
January 17, 2001

Course Outline.

January 17: First class, Introduction to the course. Review the syllabus, discuss requirements of the course. Case study, an example ISA: the LC-2. The LC-2 ISA. Assembly language syntax of the LC-2. Introduction to Assemblers.

January 22,23. Discussion: Introduction to the computing environment that will be used in the course. Further discussion of the LC-2 ISA and Assemblers. (Note: Second discussion session is in CPE 2.204 on January 22).

January 24: Introduction to the field of Computer Architecture and microarchitecture. Introduction to the science of tradeoffs. What is computer architecture (the ISA: opcodes, addressing modes, data types)? Zero address machines, one address machines, two address machines. What is microarchitecture (the data path and its control, and the microsequencer)? Overview of the basic elements of each, including structure of memory (addressing and addressibility), instruction processing, models of execution (including the Von Neumann model). The RISC phenomenon -- what it was, what it wasn't. Codes (including parity, ECC, and ASCII). System architecture issues (secondary storage, I/O).

January 29: Case study, an example microarchitecture, the LC-2. Specification of the LC-2 data path, control, state machine, microsequencer, the define file, microcode. This block of information is intended to provide a detailed comprehensive understanding of how the microarchitecture of a processor emulates the instruction set architecture.

January 30: Discussion session.

January 31: The microarchitecture of the LC-2, continued.

Lab Assignment 1 due, February 4, 11:59pm.

February 5,6: Discussion session (Note: Second discussion session is in CPE 2.204 on February 5).

February 7: Physical Memory. SRAMS, DRAMS, interleaving, unaligned accesses.

Problem Set 1 due, February 12, 5:30pm.

February 12: Virtual Memory. Address translation, Page Tables. Protection and access. TLBs. Paging and Segmentation.

February 13: Discussion session.

February 14: Virtual memory (continued).

Lab Assignment 2 due, February 18, 11:59pm.

February 19,20: Cache Memory. Caches and Cache Design. Tag store and Data Store. Set Associative, Direct Mapped, and Fully Associative, Set Size, Block Size, Write Through vs. Write Back, Replacement Algorithms, Sector Caches, Uniprocessor consistency, Virtual vs. Physical, Unified vs. Split.

February 21: Interrupts and Exceptions. Types, similarities, differences. Causes, handling, masking.

Problem Set 2 due, February 26, 5:30pm.

February 26: I/O (interrupt driven, polling, DMA, i/o processors). I/O Buses (asynchronous and synchronous). Arbitration (central vs. distributed). Bus transactions. An example.

February 27: Review for first hour exam.

February 28: Exam 1

March 5: Introduction to Performance Enhancement. Pipelining.

March 6: Discussion session.

March 7: Performance Enhancement, continued. Out-of-order execution.

March 12 through 16: No class, Spring break

March 19: Discussion session.

March 20: Discussion session.

March 21: Discussion session (Note: Second discussion session is in CPE 2.204 on March 21).

March 26: Performance Enhancement, continued. Vector processing.

March 27: Performance Enhancement, continued. Branch Prediction.

March 28: Integer Arithmetic. A special case of fixed point arithmetic. 2's complement, 1's complement, BCD, long integers, residue arithmetic. Multiplication, Booth's algorithm.

Problem Set 3 due, April 2, 5:30pm.

April 2,3: Discussion session (Note: Second discussion session is in BUR 212 on April 2).

April 4: Floating Point Arithmetic. Range vs. Precision. The IEEE Standard. Formats, gradual underflow, rounding modes, infinities, NaNs, wobble.

Lab Assignment 3 due, April 8, 11:59pm.

April 9: Issues in Multiprocessing.

April 10: Cache Coherency.

April 11: Measuring Performance. Basic metrics (e.g., SPEC95) and fundamental abuses.

Problem Set 4 due, April 16, 5:30pm.

April 16: Other Attempts to Exploit Concurrency, SIMD (both Vector and Array Processors), MIMD, VLIW, Data Flow.

April 17: Review.

April 18: Exam #2.

April 23,24,25: Case Studies: The Microarchitectures of the latest high performance microprocessors.

Lab Assignment 4 due, April 29, 11:59pm.

April 30: Introduction to Intellectual Property. Discussion of the various ways intellectual property is protected, including patents and copywrites. We will examine the various parts of a relevant patent.

May 1: Discussion session.

Problem Set 5 due, May 2, 5:30pm.

May 2: Last class: whatever you want to talk about.

May 14: Final Exam. 7 to 10pm.