EE 360N Problem Set 3 - FAQ

Spring 2001

Last Update of this Page: 3/29/01



03/29/01
Problem 1 statement has changed

Please see the problem set for the updated Problem 1.


03/28/01
More on Problem 5

Assume that:



03/28/01
Clarification for Problem 4

Assume that the virtual memory system added uses a one-level translation scheme and the page table is always resident in physical memory.


03/27/01
Clarification for Problem 4

An instruction is said to generate a page fault if a page fault occurs during the processing of that instruction.


03/27/01
Updated Problem 6

Don't forget to answer "part d" for problem 6:

(d) Show the state of the reservation stations (node tables) and the register file (with the valid bits and the tags) in part (c) after the execution of each instruction. Assume that the adder and the multiplier both have 4 entries in their associated reservation stations. Use symbolic tags for renaming as Professor Patt did in class. The structure of the reservation stations and register file (register alias table) should be the same as explained in lecture.


03/26/01
Additional Information for Problem 5



03/26/01
Clarification for Problem 6