I decided to send this to all of you since it is clear some of you are very interested in this stuff. However, it is well beyond the scope of 306, and you will see this stuff again more than once if you stick with ece. So, feel free to delete this message, if you wish, with no adverse effects as far as 306 is concerned. ...which reminds me, this is the kind of question that is fair game for the last class of the semester, the free-for-all, where every question is fair game. One of the TAs suggested I hold an extra session soon in the evening, totally optional, so you guys don't have to wait until December to ask some of these questions. If you would like me to do that, please send email to Asad Bawa (bawa@ece.utexas.edu) and let him know. If enough students want it, I will try to schedule such an optional meeting. Attendance will be totally optional, and the stuff we cover will all be outside the scope of 306 and not be tested on any exam. Let Asad know. He will collect responses and let me know. A student writes: Dr. Patt, Today I attended a seminar sponsored by IEEE that had a speaker from Micron Electronics. The speaker spent most of the presentation talking about ways to get memory to use less voltage and to be smaller. All of his examples referred to DRAM type memory. Now, the transistor level drawings that he had of DRAM didn't look quite like the memory that we have been studying in 302 (arrays of gated-D latches). Rather, a single transistor was placed on the word line that led to a small capacitor. Is this the way that most memory is being manufactured these days? Or is the Gated-D method still used? Thank you very much for your time. Sincerely, <> There are a lot of tradeoffs between DRAM and SRAM. Not really a subject for 306. Trust me, you will see it in detail before you graduate. There is a big difference between DRAM and SRAM. Our memory drawing in 306 (not 302, by the way) is much more like SRAM, although the SRAM structure is usually somewhat different (but not a lot different) from the gated-D latch. Usually consists of 4 or 6 transistors, and does have the cross-coupled gates we showed. The cross-coupling provides feedback to implement the storage of a 0 or a 1. What you heard him talk about is DRAM, where the storage is the presence (1) or absence (0) of charge on a capacitor. The one transistor is used to provide a path from that capacitor to the bit line for reading and from the bit-line to the capacitor for writing. Hope that will hold you for now. The longer answer can wait for the last lecture, or earlier if enough students want such a session some evening. Yale Patt