Dr. Patt, Could you please explain the answers for Problem 1 Part 2 Sure: 12 bits of addressibility suggests we want instructions to be 12 bits. 8 opcodes means 3 bits for the opcode, 4 registers means 2 bits for reg.num. That leaves 7 bits for the address on the page. Therefore, 128 locations per page. 10 bits of address space means 1024 locations. Since 128 locations/page, there must be 8 pages of memory. and Problem 3? How the answers were obtained? Note that the output of the AND gate that sets the gated latch is a 1 only if its two inputs are 1. This only occurs if the sign bit [15] is 0 and if one of the other bits is 1. Both are true if the value [15:0] is a positive number. Thus the latch is the P condition code. Note that the enable is the output of a seven input OR gate. Each of the seven opcodes that set condition codes (and only those seven) will make the WE of the P condition code a 1. Thanks! You're welcome. Yale Patt