Department of Electrical and Computer Engineering
The University of Texas at Austin
EE 306, Fall, 2002
Yale Patt, Instructor
TAs: Asad Bawa, Linda Bigelow, Mustafa Erwa, Lester Guillory, Kevin Major,
Abhay Pradhan, Moinuddin Qureshi, Paroma Sen, Santhosh Srinath,
Matt Starolis, David Thompson, Vikrant Venkateshwar
Problem Set #2
Due: Monday, September 23, 2002 before class
1) Problem 9 from PS 1
2) Problem 11 from PS 1
3) Problem 12 from PS 1
4) Problem 13 from PS 1
5) Problem 15 from PS 1
6) Texbook Problem 3.2 modified
A two input AND and a two input OR are both examples of a two-input logic functions.
How many different two-input logic functions are possible?
How many different three-input logic functions are possible?
How many different four-input logic functions are possible?
What is the trend you see here?
7) Texbook Problem 3.4 modified
Replace the missing parts in the circuit in Figure 1 with either a wire or no wire to give the output C a logical value of 1.
Describe a set of inputs that give the output C a logical value of 0. Replace the missing parts with wires or no wires corresponding to that set of inputs.
8) Texbook Problem 3.5 modified
Complete a truth table for the transistor-level circuit in Figure 2.
9) Texbook Problem 3.10 unmodified
Following the example of Figure 3.11a, draw the gate-level schematic of a
three-input decoder. For each output of this decoder, write the input
conditions under which that output will be 1.
NOTE: Use three-input logic gates.
10) Texbook Problem 3.11 modified
How many output lines will a five-input decoder have?
How many output lines will an eight-input decoder have?
How many output lines will an N-input decoder have? (N can be any number)
11) Texbook Problem 3.12 How many output lines will a 16-input multiplexer have?
How many select lines will this multiplexer have?
Repeat this problem for a 64 input multiplexer.
Repeat this problem for an M input multiplexer.
What property does the value M need to have?
12) Texbook Problem 3.14 modified
Given the following truth table, generate the gate-level description that implements the truth table. Follow the algorithm given in Section 3.3.4.
|0 ||0 ||0 ||0
|0 ||0 ||1 ||1
|0 ||1 ||0 ||0
|0 ||1 ||1 ||1
|1 ||0 ||0 ||1
|1 ||0 ||1 ||1
|1 ||1 ||0 ||1
|1 ||1 ||1 ||0
13) Texbook Problem 3.20 modified
Given the logic circuit in Figure 3 below, fill in the truth table for the ouput value Z.