Department of Electrical and Computer Engineering The University of Texas at Austin ECE 382N, Spring 2002 Y. N. Patt, D. N. Armstrong Exam 2 Buzzwords Block Structured ISA Atomic Unit Basic Block Straight Line Code Super Block Live-in/Live-out Arch. Visible Registers Register ports Profiling Faults Traps Code Bloat ICache Sequential Storage Trace cache Storage based on execution order Fill unit Fill unit latency Trace cache - path associativity Trace cache - partial matching Trace packing Branch promotion Simultaneous Multithreading Multithreading HEP Processor SSMT SISD, SIMD, MIMD, MISD SPMD Horizontal microprogramming VLIW Traces (Josh Fisher) Trace Scheduling Why did VLIW fail? EPIC, instruction bundles with template Decoupled Access Execute Dynamic Scheduling Out of Order HPS Precise Exceptions Memory Disambiguation Problem (Unknown address problem) Superscaler Active Window In flight instructions Reservation Stations (single vs. multiple) Dataflow Problems with Dataflow? Consistent State Code coverage in verification Restricted Data flow Register renaming CPI vs. IPC Flynn's bottleneck Checkpoint Retirement Reorder Buffer (ROB) Algorithm to issue instructions to reservation stations Register Alias Table History Register Interrupt Latency Interrupts vs. Exceptions Issue, dispatch, schedule Distributed control Irregular Parallelism Decoupled VLIW Speedup Parallelizability Static/dynamic scheduling Dense encoding of the instruction stream Dynamic Static Interface Slipstream Threads Trace cache - inactive issue Power Awareness Systolic Arrays Paritioning Synch/Asynch Logic Deeper pipelines Back to back FU's