As we did not talk about the priority based pseudo-LRU policy in detail in class, you are free to use the Victim/Next-Victim instead if you wish. Please state the policy you used in your solution.
For this problem, please serialize the accesses to the caches. So if
you miss in the L1, and hit in the L2, it takes 11 cycles. Also, start
the memory access once you know that you miss in the two caches. Assume
that it takes the time needed to access the cache to know if an access
was a hit or miss. If you had done the problem assuming that you can
access the L2 in parallel with the L1 and so on, please state this
assumption. You don't need to redo the problem.
When you receive data from memory, you can access the data as the writes to the caches are done in parallel.