These questions are to aid you in your studies. They are not to be
turned in and they do not cover all the topics covered in class after
Problem Set 5. The solutions will be posted on Monday, December 8.

From Problem Set 5
From Tanenbaum, 4th edition, Appendix B, 4.
The following binary floatingpoint number consists of a sign bit, an
excess 63, radix 2 exponent, and a 16bit fraction.
Express the value of this number as a decimal number.
0 0111111 0000001111111111

From Problem Set 5
From Tanenbaum, 4th edition, Appendix B, 5.
To add two floating point numbers, you must adjust the exponents (by
shifting the fraction) to make them the same. Then you can add the
fractions and normalize the result, if need be. Add the single
precision IEEE floatingpoint numbers 3EE00000H and 3D800000H and
express the normalized result in hexadecimal. ['H' is a notation
indicating these numbers are in hexadecimal]

From Problem Set 5
From Tanenbaum, 4th edition, Appendix B, 6.
The Tightwad Computer Company has decided to come out with a machine
having 16bit floatingpoint numbers. The model 0.001 has a
floatingpoint format with a sign bit, 7bit, excess 63 exponent and
8bit fraction. Model 0.002 has a sign bit, 5bit, excess 15 exponent
and a 10bit fraction. Both use radix 2 exponentiation. What are the
smallest and largest positive normalized numbers on both models? About
how many decimal digits of precision does each have? Would you buy
either one?

In an Omega network as presented in class, assume that there are n
inputs and n outputs. Let k be the size of each switch. For k taking
the values 2, 4, 8, and 64, answer the following questions. (Assume
the cost of each switch is k^2)
a. What is the cost of the network as a function of n?
b. What is the latency of the network?
c. Assume that n=64. What k value would you choose? Why? State
your assumptions and design point.
 We have got the following expression to compute:
a*x^6 + b*x^5 + c*x^4 + d*x^3 + e*x^2 + f*x + g
 How many operations and timesteps will the computation take on a single processor system (Use the smallest number of operations possible)?
 How many operations and timesteps will the computation take on a multiprocessor system with 4 processors? (Use the smallest number of operations possible)
 What is the speedup of the multiprocessor system over a single processor?

The state diagram for the Goodman cache consistency scheme makes one
assumption about the size of the cache blocks. What is it? (Hint:
Focus on the case in which a block is in the DIRTY state and a BW
signal comes in. Where do we go? Why?) If that assumption is not made,
what will be the change in the state diagram? Draw the new state
diagram.