EE 360N - Programming Assignment 4 Clarifications

  1. Clarification on the values of the control signals. We will check the values of the internal pipeline latches generated by your simulator, so make sure you follow these conventions.

  2. If DCACHE is not enabled (V.DCACHE.EN signal is 0), the data output by the DCACHE should be set to 0x0000.

  3. Control store entries corresponding to invalid opcodes (opcodes 1010 and 1011) should be set to all 0.

  4. SR.IR should be 16 bits in figure 5 (Memory Stage). SR.IR is only used for displaying IR value for debugging.

  5. The shifter should perform a left shift if IR[5] is 1 and IR[4] is 0.

  6. Will you check the values in pipeline latches even if the latches are invalid?

    If the pipeline latches in a stage is invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.