The goal of this lab assignment is to extend the LC-3b simulator you wrote in Lab 2 to handle virtual memory, exceptions, and interrupts. You will augment the existing LC-3b microarchitecture with facilities for virtual to physical address translation and access protection checks. You will also provide microarchitectural support for detecting and handling timer interrupts, page fault exceptions, and protection exceptions.
In Lab 3, the address space of the LC-3b is divided into pages of 512 locations. The LC-3b virtual address space has 128 pages, while physical memory has 32 frames. Virtual pages 0-23, which are reserved for the operating system, will be mapped to frames 0-23 and will always be resident in physical memory. Frames 24-31 are available for swapping virtual pages of user programs. There are two modes of operation: supervisor and user. Virtual pages 0-23 cannot be accessed unless the LC-3b is in supervisor mode. Since user programs operate in user mode, they cannot access those pages. Thus the user virtual memory space is 104 pages (pages 24-127).
The input to this new simulator will be:
New shell code A modified shell code has been written for you:
lc3bsim3.c (If you used the old shell code for Lab 2, download lc3bsim3_old.c)
This shell code has the capability of loading the page table into memory. You will need to copy and paste the code you wrote for Lab 2 into this new shell code.
Note that a new command line parameter has been added: the pagetable. To run the simulator, type:
lc3bsim3 <micro_code_file> <page table file> <program_file_1> <program_file_2> ...
The first parameter is the microcode file as before. The second parameter is the page table in LC-3b machine language. Note that since the page table is in physical memory, the first line of this file should have a physical address. For all the program files, (including the interrupt & exception handlers) which are in virtual memory, the first line should have a virtual address.
This Lab consists of 3 parts, which we will describe in detail:
1. Adding support for virtual memory
2. Adding support for timer interrupts
3. Adding support for page fault and protection exceptions
The Page Table
The page table should be placed at the beginning of frame 8 of physical memory. A page table entry (PTE) contains only 9 bits of information, but for convenience, it is represented in a full 16 bit word. Thus one page table entry occupies two memory locations. The format of each page table entry is as follows:
PFN = PTE[13:9], the page frame number
P = PTE, the protection bit
P=0 -> page can only be accessed in supervisor mode
P=1 -> user has full rights to the page
V = PTE, the valid bit (V=1 for a valid page)
M = PTE, the modified bit (M=1 if page has been written)
R = PTE, the reference bit
R=1 -> page has been referenced since last timer interrupt
R=0 -> otherwise
All other bits are set to zero.
Page Table Access from the Datapath
During the execution of instructions, your microcode will have to convert virtual addresses to physical addresses, as well as modify PTE's when necessary. To make address translation possible, we have added more structures to the datapath. We have added these registers: Page Table Base Register (PTBR) and Virtual Address Register (VA). The PTBR points to the first entry of the page table in physical memory. It's used to access a particular PTE during translation. To read from this register onto the bus, you should assert the GatePTBR signal. The VA register is a temporary register to hold the current address under translation. To read the VA register onto the bus and to write to the VA register from the bus, you should assert the GateVA and LD.VA control signals respectively.
Assume that at the beginning of each address translation phase the virtual address is located in the MAR, and if the operation is a write, a source register holds the data to be written. Address translation consists of the following steps:
To add support for virtual memory, you first need to determine when you need to perform the address translation. Then, you will need to determine how to modify the state diagram so that it supports a "micro-subroutine" written in microcode to translate addresses. You will also need to determine how to return back to the correct state once address translation is complete. For this, you need to augment the microsequencer. You are free to add new control signals, gates, muxes, temporary registers as you wish as long as you fully document your changes.
In this lab, a timer interrupt will occur at cycle 500. When the timer generates an interrupt, the microarchitecture may be in the middle of executing an instruction. You need to decide exactly when the interrupt is detected and add the necessary microarchitectural support to handle interrupts. When the interrupt is detected the following actions will be taken by the processor:
1. The privilege mode (most significant bit of the PSR, program status register) is set to 0, which indicates supervisor-level privilege. Interrupt service routine will be executed with supervisor-level privilege.
2. R6 is set to the supervisor stack pointer if that is not already the case.
3. The old PSR (PSR before PSR is set to 0) and PC are pushed onto the supervisor stack. Supervisor stack pointer is decremented on each push. Note that the supervisor stack is different from user stack. Interrupt service routines can access the supervisor stack using R6. You should initialize the supervisor stack pointer to address 0x3000. Note that R6 will refer to the user stack while your program is running. It will refer to the supervisor stack while the interrupt service routine is being executed. If the system is in user mode when an interrupt is detected, the microarchitecture should transparently switch R6 so that it points to the supervisor stack. You need to implement this "stack switching" in microcode. You will need to modify the datapath, add new states to the state machine, and possibly add new control signals to support this operation. You may add registers to the datapath to save and restore user and supervisor stack pointers.
4. The interrupting event supplies its 8-bit interrupt vector (INTV). The interrupt vector for the timer is 0x01.
5. The processor left-shifts the interrupt vector one bit, yielding x02, and adds it to the base address of the interrupt/exception vector table (x200), yielding the address of the memory location (x0202), which contains the starting address of the interrupt service routine.
6. The contents of memory location x0202, which should be x1200 for this assignment, are read and loaded into the PC.
7. The processor begins execution of the interrupt service routine.
The first step in adding support for interrupts is to determine how the state diagram of the LC-3b can be modified to handle interrupts. You will have to augment the microsequencer with additional logic to sequence these new states, and extend the existing microinstructions with additional bits for both the microsequencer and the datapath. You may augment current microinstruction fields and add new fields. You may also add new logic to the datapath. You are free to implement this as you wish, but you must document your method.
Next, you have to implement an instruction for returning from an interrupt. This will be used in the interrupt service routine to transfer control back to the interrupted program. This instruction, called RTI (return from interrupt), has the opcode 1000, and pops the old PC and PSR off the supervisor stack. If the RTI transfers control back to a user-level program, then the microcode should switch the stack pointer back so that R6 points to the user stack. (See the ISA reference for details on the RTI instruction)
Page Fault Exception
If the page accessed by a user program is not valid (not in physical memory), then a page fault exception will occur. Exception handling for page faults is very similar to interrupt handling as described above with an important difference: the exception-causing instruction should not be allowed to complete before the exception is handled. Hence, the memory access that causes the page fault exception also should not be allowed to complete. You will need to change the mode of the machine to supervisor, switch to the supervisor stack, push the decremented PC and PSR on the supervisor stack and load the PC with the address of the exception service routine. The exception vector for page fault exception is x02. You can store the exception vector in a separate EXCV register and add this register to the interrupt/exception vector table base register to get the address of the location that contains the starting address of the exception service routine. You are free to implement this as you wish, but keep in mind the possibility of combining the states used for initiating the interrupt service routine and those used for initiating the exception service routine.
You will also write the exception service routine for the page fault. This routine should start at memory location x1400. For the purposes of this assignment, the exception service routine will simply halt the machine. However, don't rely on this. We can test your simulator by replacing your exception routine with our routine which returns from the exception handler using the RTI instruction instead of halting the machine. Upon return from the exception handler, the instruction that caused the exception should be re-executed.
Protection exceptions occur only when the machine is in user mode, and a memory page whose PTE protection bit is set to 0 is accessed. The memory access that causes a protection exception should not be allowed to complete. Similar to a page fault, the processor takes the necessary steps and jumps to a handler routine to handle the protection exception. Exception vector for the protection exception is x04. The exception handler for the protection exception is located starting at x1600. This routine should halt the machine. However, as with the page fault exception, do not assume that the machine will always be halted after a protection exception occurs.
Tips on getting started
We suggest that you implement each of the three functionalities and test them one by one before putting them all together. This should make the debugging process simpler. For example, you can start by implementing the virtual memory support. Once you test and make sure that address translation works, you can move on to adding support for interrupts and exceptions. When designing the mechanisms to support interrupts and exceptions keep in mind that they are handled very similarly. In your microcode, states for pushing the PSR and PC on stack and loading the address of handler routines could be shared for both exception and interrupt handling.
The user program in page 24 should do the following: calculate the
sum of the first 20 values stored in the memory locations beginning
with xC000 (notice this is on page 96). This sum should then be stored
at xC014. Then the program should jump to the address pointed to by
this sum. Page 96 contains data to be used by the program on page
24. The following numbers should be stored there:
x0012, x0011, x2F39, x1023, x1002, x00F6, x0912, x0123, x0456, x0789, x0ABC, x0DEF, x0000, x0001, x0002, x0003, x0004, x0005, x0006, x0007.
These should be loaded into page 96 on initialization of the simulator.
The interrupt service routine must traverse the entire page table, clearing the R bits of each PTE. You may assume when writing this code that the start address of the page table is fixed.
The exception handlers you will submit should simply halt the machine.
Initial Page Table Contents
The page table will be initialized upon simulator start-up. It should look as follows:
Pages 0-23 are in frames 0-23. They are valid and inaccessible by the user.What To Submit Electronically
Page 24 is in frame 25. It is valid and accessible by the user.
Page 96 is in frame 28. It is valid and accessible by the user.
Page 126 is in frame 29. It is valid and accessible by the user. This page contains the user stack.
All other pages are invalid.
How to generate the dumpsim file
Dump the memory locations containing the page table entries once before the 500th cycle, once after the ISR is done, and finally after the page fault halts the execution of the program (you should get a page fault after the jump). Also, dump memory location x3814 (corresponding to which virtual address?) and the current registers after the page fault.
Things To Consider
The user stack should start at address 0xFE00 and the supervisor stack should start at virtual address 0x3000.