Department of Electrical and Computer Engineering
The University of Texas at Austin
EE 360N, Spring 2003
Study Questions (covering some of the topics covered in class after Problem Set 5)
Due date: Not to be turned in
Yale N. Patt, Instructor
Hyesoon Kim, Moinuddin Qureshi, Onur Mutlu, Santhosh Srinath, TAs
These questions are to aid you in your studies. They are not to be
turned in and they do not cover all the topics covered in class after
Problem Set 5.

In an Omega network as presented in class, assume that there are n
inputs and n outputs. Let k be the size of each switch. For k taking
the values 2, 4, 8, and 64, answer the following questions. (Assume
the cost of each switch is k^2)
a. What is the cost of the network as a function of n?
b. What is the latency of the network?
c. Assume that n=64. What k value would you choose? Why? State
your assumptions and design point.
 We have got the following expression to compute:
a*x^6 + b*x^5 + c*x^4 + d*x^3 + e*x^2 + f*x + g
 How many operations and timesteps will the computation take on a single processor system (Use the smallest number of operations possible)?
 How many operations and timesteps will the computation take on a multiprocessor system with 4 processors? (Use the smallest number of operations possible)
 What is the speedup of the multiprocessor system over a single processor?

The state diagram for the Goodman cache consistency scheme makes one
assumption about the size of the cache blocks. What is it? (Hint:
Focus on the case in which a block is in the DIRTY state and a BW
signal comes in. Where do we go? Why?) If that assumption is not made,
what will be the change in the state diagram? Draw the new state
diagram.