A student writes:

     i had some small questions. 

     first, are we going to be tested on material from the first test? 

     second, how much do we need to know about the .EXTERNAL pseudo-op? 
     the book says it is not part of the lc-3 pseudo-ops, so do we need 
     to know hwo it could be used if it was an lc3 pseudo-op? 

     also, are subroutines and stuff you teach on monday going to be 
     on the exam? 

     lastly, about kbdr kbsr and 
     ddr dsr, they have memory-mapped addresses. 
     is the data within these memory-
     mapped locations the address for the registers? or is this data used to 
     identify the register some other way? 
     if it is the address, why do we even need it? 
     i mean if we are using addresses to identify the registers, 
     why put the addresses into other addresses?
     thats it.

     << name withheld to protect a man with some small problems >>

So, I will deal with these one by one.

1. Engineering courses have a way of building on what you already know. So, if you forget what you learned before the first test, you will probably flunk every test after that. Certainly, we will emphasize what we have studied recently. But we will undoubtedly bring into the problems and their solutions material from before the first test.

In fact, in the review session tonight, I showed an AND gate with bit[15] and bit[14] as inputs. AND gates were certainly part of what we learned before the first test.

2. .EXTERNAL. You are not using .EXTERNAL in your LC-3 programming, so you don't need to know it in depth. I could, however, test you on it to the extent that we discussed it in lecture. If you were at the review session tonight and understood what I said about it in response to a question, then I would say you are sufficiently knowledgeable about it to not worry about it.

3. What we did on Monday will not be on the exam. The exam covers up to where we left off last Wednesday. I do not think it is reasonable for me to explain something on Monday and then put it on the exam two days later. So, that stuff will have to wait for the final.

4. I am not clear exactly what you are asking about the I/O device registers. They have addresses, so I can access them in the same way I access memory locations -- with loads and stores. The addressing mode determines how I construct the address of the device registers.

From your question, I am not sure you have the concept right. The data within these memory mapped locations are NOT addresses. I am concerned you are confusing locations in your program that contain the addresses of the device registers with the device registers themselves. The first example in the book is in the middle of page 203 in the book.

On line 5, you note you have a location A that contains xFE00 and on line 6, you have a location B that contains xFE02. A and B are not memory-mapped I/O registers. They are simply memory locations in your program. They contain the addresses of KBSR and KBDR, which are memory-mapped addresses. That is, the address of the register KBSR is xFE00. The address of the register KBDR is xFE02. These are NOT memory locations. They are registers that are part of the Keyboard Input system. There are NO memory locations having addresses xFE00 or xFE02.

Finally, the data in these registers are as follows: In KBDR the data is an ASCII code in bits[7:0], if someone hit a key. In KBSR, the data is the Ready bit in [15] and the IE bit in [14].

If the above is still not clear, please see your TA during office hours....or see me.

Good luck on the exam.

Yale Patt