Department of Electrical and Computer Engineering
The University of Texas at Austin
EE 306, Fall 2004
Problem Set 1b
Due: 13 September, before class
Yale N. Patt, Instructor
Siddharth Balwani, Linda Bigelow, Tommy Buell, Jeremy Carrillo, Aamir Hasan,
Danny Lynch, Rustam Miftakhutdinov, Veynu Narasiman, Vishal Parikh, Basit Sheikh, TAs
You are encouraged to work on the problem set in groups and turn
in one problem set for the entire group. Remember to put all
your names on the solution sheet. Also remember to put the name
of the TA in whose discussion section you would like the problem
set turned back to you.
If n and m are both 4-bit 2's complement numbers, and s is the 4-bit result of adding them together, how can we determine, using only the logical operations described in Section 2.6, if an overflow has occurred during the addition? Develop a "procedure" for doing so. The inputs to the procedure are n, m, and s, and the output will be a bit pattern of all zeros (0000) if no overflow occurred and 1000 if an overflow did occur.
- (2.40 a,b,c)
Write the decimal equivalents for these IEEE floating point numbers.
- 0 10000000 00000000000000000000000
- 1 10000011 00010000000000000000000
- 0 11111111 00000000000000000000000
- (2.50 b,d)
Perform the following logical operations. Express your answers in hexadecimal notation.
- xABCD OR x1234
- x00FF XOR x325C
Fill in the truth table for the equations given. The first line is done as an example.
Q1 = NOT (NOT(X) OR (X AND Y AND Z))
Q2 = NOT ((Y OR Z) AND (X AND Y AND Z))