A student writes: Respected Sir, I had a few quick questions after class today. I took a diversion, so couldn't ask you there. a) In page-4 of your "Processor Speed-ups" handout (the page with lots of FORTRAN code on it). (1) What is the difference between MOVI and MOVA instructions? MOVI loads an immediate, MOVA loads an address. These opcodes are my concoction, although I have certainly seen similar stuff in several assembly language manuals. (2) Under the "Vector" heading, you have used "VST" twice, in line-2 and line-7. Is that a typo, or is it actually something meaningful, i.e. Vector Stride register is somehow related to Vector Store? Oops. I got to be very careful with you. Yup, VST means Vector Stride Register when I want it to mean that, and Vector Store instruction when=20 I want it to mean that. And since it is my computer, it reads my mind. To be less entertaining, I could have argued: As an operand, it must mean vector stride register, and as an instruction, it must mean vector store instruction, and in assembly language, opcodes tend to come first, and operands later. But, the real truth is: I was sloppy. b) Do we have more than one bus in case of a pipeline? I have a very unclear idea here. Or is it that we use just a single bus in such a way that when the bus is not being used by an instruction, another instruction can use it for its purposes? In a pipeline, I need a separate bus between each pair, stage i and = stage i+1. c) This one's a bit stupid. I don't answer stupid questions. Page-2 of your handout (the vector machine diagram) has several registers like NIP, CIP, LIP, XA, VL, etc. but I don't know what they are. Did you already explain that in class Nope, I did not. ...and shame on me, I don't have the paper handy so I can't look it up. Best reference for the Cray I paper is the one by Russell in January, 78 (I believe) issue of Communications of the ACM, back in the days when Comm. ACM published research papers. That was a special issue edited by Sam Fuller that has a lot of good historical comp.arch papers in it. ...if you can ever lay your fingers on it. I can try to decipher some of these. NIP, CIP, and LIP are probably three variants of the PC. Recall Intel called it IP. Probably Cray did also. and Next, Current, and Last would make sense to me. ...particularly since they are next to the Instruction Buffers. I think I would have drawn the arrows differently to make it more expressive. VL is probably vector length register. P, given the loop with the +1 and the arrow pointing to the instructions could be the PC. How it is different from CIP I don't know. VM, RTC, and XA I do not know. If anyone does, or looks it up and finds it, please share it with the rest of us. Hope all this helps, in spite of my cop-out on the last one. Yale Patt (and I unknowingly missed that) or do you plan to explain that in detail later? Thank you very much. With kind regards, <>