For this assignment, you will write a simulator for the LC-3b. The simulator will take two input files:
Note: The file isaprogram is the output you generated in Lab Assignment 1. This file should consist of 4 hex characters per line. Each line of 4 hex characters should be prefixed with '0x'. For example, the instruction NOT R1, R6 would have been assembled to 1001001110111111. This instruction would be represented in the isaprogram file as 0x93BF. The file ucode is an ASCII file that consists of 64 rows and 35 columns of zeros and ones.
The simulator is partitioned into two main sections, the shell, which allows a user to control the simulator, and the simulation routines, which carry out the simulation.
The purpose of the shell is to provide the user with commands to control the execution of the simulator. In order to extract information from the simulator, a file named dumpsim will be created to hold information requested from the simulator. The shell supports the following commands:
The simulation routines carry out the cycle-by-cycle simulation of the input LC-3b program. The simulation of any cycle is based on the contents of the current latches in the system. The simulation consists of two concurrently executing phases:
The microsequencer phase uses 9 bits from the microinstruction register and appropriate literals from the datapath to determine the next microinstruction. Function eval_micro_sequencer evaluates this phase.
The datapath phase uses 23 bits of the microinstruction to manipulate the data in the datapath. Each microinstruction must be literally interpreted. For example, if the GateMDR bit is asserted, then data must go from the MDR onto the bus. You must also establish an order for events to occur during a machine cycle. For example, data should be gated onto the bus first, and loaded into a register at the end of the cycle. Simulate these events by writing the code for functions eval_bus_drivers, drive_bus and latch_datapath_values.
We will assume a memory operation takes five cycles to complete. That is, the ready bit is asserted sometime at the end of the fourth cycle. Function cycle_memory_IO emulates memory and IO.
What To Do
The shell has been written for you. From your ECE LRC account, copy the following file to your work directory:
lc3bsim.cAt present, the shell reads in the microcode and input program and initializes the machine. It is your responsibility to write the correct microcode file and to augment the shell with the simulation routines that simulate the activity of the LC-3b. In particular, you will be writing the code to perform the activities of the three phases (datapath, microsequencer, memory) described above.
Add your code to the end of the shell code. Do not modify the shell code.
The accuracy of your simulator is your main priority. Specifically, make sure the correct microarchitecture structures sample the correct signals. It is your responsibility to verify that your simulator is working correctly. It is suggested that you start out doing this by writing a one instruction program and simulating this program cycle by cycle using the rdump command to verify that data is being manipulated properly each cycle.
Because we will be evaluating your code on linux, you must be sure your code compiles on an ECE linux machine (linux01 - linux16.ece.utexas.edu) using gcc with the -ansi flag. This means that you need to write your code in C such that it conforms to the ANSI C standard. You should also make sure that your code runs correctly on one of the ECE linux machines.
- You do not need to worry about the interface to the keyboard and the display.
- Assume that the device registers will only be accessed using LDW and STW.
- Assume that the programmer will never give a store inctruction involving KBDR or a load instruction involving DDR.
- When a store is issued to location 0xFE00 (KBSR) then the value should NOT get written to memory location 0xFE00 but it should only be written to KBSR. Same applies to the other 2 writable I/O device registers.
- It takes 2 cycles to access the I/O registers.That is, the I/O Ready bit is asserted sometime at the end of the first cycle, gets latched at the clock edge, and gets used by the microsequencer during the second cycle. The I/O ready signal is an output of the Address Control Logic. The Ready bit shown in the State Diagram is the logical OR of the Ready output from the memory and the I/O ready signal from the Address control logic.
You will submit your lab assignment electronically. Instructions will be posted on the course web page on how to do so. You will submit the following: