EE 382N - Handouts and References
Spring 2004
- Papers
- The papers in class 4/26/2004
- J. E. Smith, "Characterizing computer performance with a single number ,"Communications of the ACM Volume 31 , Issue 10 (October 1988) [pdf]
- The papers in class 4/19/2004
- Sarita V. Adve, Mark D. Hill, "Implementing Sequential Consistency In Cache-Based Systems,"Proc. of the 1990 Int'l Conf. on Parallel Processing.[pdf]
- Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar, "Multiscalar processors,"Proceedings of the 22nd annual international symposium on Computer architecture (1995). [pdf]
- L. Lampon,"How to make a multiprocessor computer that correctly executes multiprocess programs," IEEE Trans. Comput., C-28(9):241 248, September 1979.
- The papers in class 4/14/2004
- Todd M. Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," Proceedings of the 32nd International Symposium on Microarchitecture 1999.[pdf]
- G. Savransky, R. Ronen, and A. Gonzalez, " Lazy Retirement: A Power Aware Register Management Mechanism,"Workshop on Complexity-Effective Design 2002. [pdf]
- Pentium 4 processor
- Glenn Hinton, Dave Sager, Mike Upton, Darrell Boggs, Doug Carmean, Alan Kyker,Patrice Roussel, "The Microarchitecture of the PentiumŪ 4 Processor", Intel Technology Journal, 2001. [pdf]
- Scheduling paper
- Mary D. Brown, Jared Stark, and Yale N. Patt,
"Select-Free Instruction Scheduling Logic,"
Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, Austin, Texas, December 2001. [pdf]
- Jared Stark, Mary D. Brown, and Yale N. Patt,
"On Pipelining Dynamic Instruction Scheduling Logic,"
Proceedings of the 33rd ACM/IEEE International Symposium on Microarchitecture, Monterey, California, December 2000. [pdf]
- Philip C. Treleaven, David R. Brownbridge, and Richard P. Hopkins,
"Data-Driven and Demand-Driven Computer Architecture," ACM Computing Surveys , 1982.[pdf]
- The papers in class 2/25/2004:
- Stephen Melvin and Yale Patt,
"Exploiting Fine-Grained Parallelism through Combined Hardware and Software Techniques,"
Proceedings of the 18th International Symposium on Computer Architecture,
May 1991. [pdf]
- Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,"
Proceedings of the 29th ACM/IEEE International Symposium on Microarchitecture,
Paris, France, November 1996.[ps]
- Eric Sprangle and Yale N. Patt,
"Facilitating Superscalar Processing via a Combined Static/Dynamic Register Renaming Scheme,"
Proceedings of the 27th International Symposium on Microarchitecture,
San Jose, California, November 1994. [pdf]
- Mario Daniel Nemirovsky, Forrest Brewer, Roger C. Wood
"DISC: dynamic instruction stream computer,"
Proceedings of the 24th International Symposium on Microarchitecture, 1991
[pdf]
- Trace Cache :
- Sanjay J. Patel, Marius Evers, and Yale N. Patt,"Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing,"Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, Spain, June 1998.[pdf]
-
Daniel H. Friendly, Sanjay J. Patel, and Yale N. Patt,
"Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism,"
Proceedings of the 30th ACM/IEEE International Symposium on Microarchitecture,
Research Triangle Park, North Carolina, November 1997. [pdf]
- Eric Rotenberg, Steve Bennett, Jim Smith,
"Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching,"
In Proceedings of the 29th International Symposium on Microarchitecture, December 1996.
[pdf]
- Bryan Black, Bohuslav Rychlik, and John Paul Shen,
"The Block-based Trace Cache,"
Proceedings of the 26th Annual Intl. Symposium on Computer Architecture, 1999
[pdf]
-
Sanjay J. Patel and Steven S. Lumetta,
"rePLay : a Hardware Framework for Dynamic Program Optimization,"
University of Illinois Technical Report, CRHC-99-16, December 1999.[ps]
- The first two HPS papers mentioned in class, 1/20/2004 :
- Yale Patt, Wen-mei Hwu, and Michael Shebanow. "HPS, a new microarchitecture: rationale and introduction,"
Proceedings of the 18th annual workshop on Microprogramming,
December 1985. [ pdf]
- Yale Patt, Stephen W. Melvin, Wen-mei Hwu, and Michael Shebanow. "Critical issues regarding HPS, a high performance microarchitecture,"
Proceedings of the 18th annual workshop on Microprogramming,
December 1985.[ pdf]
- The references mentioned in class, 1/21/2004:
- John Swensen and Yale Patt. "Fast temporary storage for serial and parallel execution," Proceedings of the 14th International Symposium on Computer Architecture, June 1987. [ pdf ]
- Stephen W. Melvin and Yale Patt,"A clarification of the dynamic/static interface,"
Proceedings of the 20th Annual Hawaii International Conference on System Sciences, 1987.
- Patt, Y.N. Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE , vol. 89, no. 11, November 2001, pp. 1553-1559. [pdf]
- Patt, Y.N., Patel, S.J., Evers, M., Friendly, D.H., Stark, J. One billion transistors, one uniprocessor, one chip. Computer, vol. 30, no. 9, September 1997, pp. 51 -57. [pdf]
- B. Ramakrishna Rau and Joseph A. Fisher: Instruction-Level Parallel Processing: History, Overview, and Perspective, The Journal of Supercomputing 7(1-2), 1993.
[Technical Reports]
- W. Buchholz and R.S. Ballance, Planning a Computer System, McGraw-Hill, 1962.
- J.E. Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman
& Company, 1970.
- D.P. Siewiorek, C.G. Bell, and A. Newell, Computer Structures: Principles
and Examples, McGraw-Hill, 1982. (Chapters 18 and 19 deal with Tomasulo).