profiling representativeness (of data) compile-time (static) runtime (dynamic) levels of transformation algorithm ISA microarchitecture opcode prefix property addressing modes data types addressability byte-addressable address space endianness (big-endian/little-endian) fixed length vs. variable length uniform vs. non-uniform decode memory-mapped I/O operate instructions logically complete arithmetic/logical shift 2-pass assembler pseudo-op label data movement instructions control instructions condition codes 0, 1, 2, 3 address machine load/store ISA fetch hardware interlock semantic gap microsequencer control store microinstruction datapath state machine VLIW compatibility pipelining precise exceptions interrupts exceptions critical path design bread and butter design balanced design SRAM DRAM capacitor refresh page mode row address (RAS) column address (CAS) chip enable ECC parity Hamming Code CRC check banked memory interleaving unaligned access balance set working set swap in/swap out page frame resident paging page in/page out thrashing page table mapping virtual to physical addresses PTE PSR privelege level protection virtual memory physical memory address translation VPN PFN TLB valid bit reference bit modify bit page table base register limit register system space user space access control violation (ACV) page fault (TNV) segmentation segment register linear address cache memory spatial locality temporal locality cache line (block) temporal locality spatial locality tag index direct-mapped cache fully-associative cache set-associative cache tag/data store dirty bit cache hit/miss hit ratio RAM direct access memory sequential access memory associative access CAM writeback/write through allocate on write miss sector cache replacement policy (LRU, FIFO, random, victim/next-victim) key transformation virtually-indexed, virtually-tagged cache physically-indexed, physically-tagged cache virtually-indexed, physically-tagged cache cold start effect context switch cache consistency/coherency inclusion property multiple levels of caches